Three-dimensional multichip module systems

• US 5,111,278 A
• Filed: 03/27/1991
• Issued: 05/05/1992
• Est. Priority Date: 03/27/1991
• Status: Expired due to Fees

• Current Assignee: Integrated System Assemblies Corp.
• Original Assignee: Integrated System Assemblies Corp.
• Inventors: Eichelberger, Charles W.
• Primary Examiner(s): EPPS, GEORGIA Y
• Application Number:
  US07/676,936
• Time in Patent Office: 405 Days
• Field of Search: 357/75, 357/74, 357/65, 357/71, 357/55, 357/80, 357/72, 357/81
• US Class Current: 257/698
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01011 Sodium [Na]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12033 : Gunn diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0272 : Adaptations for fluid transport, e.g. channels, holes
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/09509 : Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09536 : Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 3/4623 : the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards H05K3/462 takes precedence
• CPC Class Codes: H05K 3/4644 : by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602

Abstract

Multichip integrated circuit packages and methods of fabrication, along with systems for stacking such packages, are disclosed. In one embodiment, the multichip package has an array of contact pads on an upper surface thereof and an array of contact pads on a lower surface thereof. Connection means are provided for electrically coupling at least some of the contact pads on each package surface with selected ones of the contact pads on the other surface, or selected interconnection metallization which is disposed between integrated circuits located within the package. The contact pads of each surface array are preferably equal in number and vertically aligned such that multiple multichip packages may be readily stacked, with a conductive means disposed therebetween for electrically coupling the contact pads of one package to the pads of another package. In addition, various internal and external heat sink structures are provided which facilitate dissipation of heat in a multichip package or in a stack of multichip packages. Specific processing methods for each of the various multichip modules and stack systems disclosed are described herein.

Claims

1. A multichip integrated circuit package having an upper surface and a lower surface, said package comprising:

a substrate;

a plurality of integrated circuit chips disposed on an upper surface of said substrate, said integrated circuit chips each having at least one interconnection pad on a top surface thereof;

encapsulant surrounding said integrated circuit chips, said encapsulant surrounding said integrated circuit chips, the integrated circuit chips and having a plurality of via openings therein, said openings being aligned with at least some of said interconnection pads;

a pattern of interconnection conductors disposed above the upper surface of said encapsulant so as to extend between at least some of the openings therein and so as to provide electrical connection to at least some of the interconnection pads through the said openings; and

conductive means disposed within said substrate and said encapsulant so as to provide electrical connection between the lower surface of said substrate and the interconnection conductors disposed above the upper surface of said encapsulant, said conductive means being disposed within said encapsulant so as to pass between said plurality of integrated circuit chips.

2. The integrated circuit package of claim 1, further comprising an array of conductor pads disposed on the lower surface of said integrated circuit package.

3. The integrated circuit package of claim 2, further comprising:

an array of conductor pads disposed on the upper surface of said integrated circuit package; and

said conductive means being disposed within said substrate and said encapsulant so as to provide electrical connection between at least some of said lower surface array of conductor pads and at least one of the pads of the upper surface array of conductor pads and the interconnection conductors disposed above the upper surface of said encapsulant, said conductive means also providing electrical connection between at least some of said upper surface array of conductor pads and at least one of the pads of the lower surface array of conductor pads and the interconnection conductors disposed above the upper surface of said encapsulant.

4. The integrated circuit package of claim 3, wherein the upper surface and lower surface of said substrate are in substantially parallel planes, and wherein said package further comprises at least one cooling channel disposed within said substrate.

5. The integrated circuit package of claim 4, wherein said package further includes a plurality of cooling channels disposed within said substrate, each of said channels being oriented substantially parallel to the planes of said upper and lower surfaces.

6. The integrated circuit package of claim 3, wherein said upper surface array of conductor pads is disposed over substantially the entire upper surface of said integrated circuit package, and wherein said lower surface array of conductor pads is disposed over substantially the entire lower surface of said integrated circuit package.

7. The integrated circuit package of claim 3, wherein said upper surface array of conductor pads and said lower surface array of conductor pads each has an equal number of conductor pads therein, and wherein each conductor pad of said upper surface array of conductor pads is aligned with a respective conductor pad of said lower surface array of conductor pads.

8. The integrated circuit package of claim 3, wherein said upper surface of said package comprises the upper surface of said encapsulant, and wherein the lower surface of said package comprises the lower surface of said substrate.

9. The integrated circuit package of claim 3, wherein said conductive means electrically connects each of said pads in said lower surface array of conductor pads to at least one of a pad in said upper surface array of conductor pads and a conductor of the interconnection conductors disposed on the upper surface of said encapsulant, and wherein said conductive means electrically connects each of said pads in said upper surface array of conductor pads to at least one of a pad in the lower surface array of conductor pads and a conductor of the interconnection conductors disposed on the upper surface of said encapsulant.

10. The integrated circuit package of claim 1 wherein the conductive means includes metalized via holes in said encapsulant extending substantially to the upper surface of said substrate in the area of said encapsulant between said plurality of integrated circuit chips.

11. The integrated circuit package of claim 10, wherein said conductive means includes metalized through holes disbursed throughout said substrate, each of said through holes extending from the upper surface of said substrate to the lower surface of said substrate, and each metalized through hole having a conductor pad electrically coupled thereto at the lower surface of said substrate, said conductor pads comprising an array of conductor pads on the lower surface of said package.

12. The integrated circuit package of claim 11, wherein said conductive means includes a plurality of distribution conductors, said plurality of distribution conductors being disposed on the upper surface of said substrate and positioned to electrically connect at least some of said metalized via openings positioned between said integrated circuit chips and said metalized through holes in said substrate.

13. The integrated circuit package of claim 12, wherein said conductive means includes means for electrically coupling selected conductor pads of said array of conductor pads on the upper surface of said package with at least some of said metallized via openings disposed in said encapsulant between said integrated circuit chips.

14. The integrated circuit package of claim 13, further comprising at least one cooling channel disposed within said substrate.

15. The integrated circuit package of claim 3, wherein each pad of a plurality of conductor pads of said lower surface array of conductor pads is electrically coupled via said conductive means to a respective one of said pads in said array of conductor pads on the upper surface of said package.

16. The integrated circuit package of claim 1, wherein said conductive means includes metallization disposed within columns provided within said package extending from the upper surface of said package to the lower surface of said package, said columns being disposed within said package so as to avoid passing through one of said plurality of integrated circuit chips.

17. The integrated circuit package of claim 16, wherein the substrate comprises a thin metal.

18. The integrated circuit package of claim 17, wherein said metalized columns pass through said metal substrate and are isolated therefrom by said encapsulant.

19. The integrated circuit package of claim 16, wherein said substrate has a plurality of cooling channels disposed therein, each of said channels being oriented substantially parallel to the upper and lower substrate surfaces.

20. The integrated circuit package of claim 1, further including:

a dielectric layer overlying said encapsulant and a portion of said interconnection conductors, said dielectric layer also including a plurality of via openings therein aligned with at least some of said interconnection conductors underlying said dielectric layer; and

said pattern of interconnection conductors being partially disposed above said dielectric layer and extending between at least some of the openings in said dielectric layer so as to provide electrical connection with interconnection conductors underling said dielectric layer.

21. The integrated circuit package of claim 1, wherein the substrate comprises material selected from the group consisting of glass, ceramic, plastic, silicon and composites.

22. The integrated circuit package of claim 1, wherein the substrate comprises material selected from the group consisting of alumina and aluminum nitride.

23. The integrated circuit package of claim 1, wherein said encapsulant is a polymer material selected from the group consisting of thermoplastic and thermoset materials.

32. The multichip module stack system of claim 3, wherein said heat sink structure includes an array of conductor pads on the upper surface thereof and an array of conductor pads on the lower surface thereof, each of said conductor pads being coupled to one of said vertically oriented metalized columns.

33. The multichip module stack system of claim 32 ,wherein said conductor pads in said upper and lower surface arrays of conductor pads are each positioned to align with a conductor pad of an adjacent one of said plurality of packages within said stack system.

42. The heat sink structure of claim 4, wherein each of said plurality of metallized columns has a layer of metallization disposed therein extending from said upper substrate surface to said lower substrate surface, said column of metallization facilitating electrical connection through said heat sink structure.

43. The heat sink structure of claim 42, wherein said substrate comprises material selected from the group consisting of glass, metal, ceramic, plastic, silicon and composites.

44. The heat sink structure of claim 42, wherein at least one of said upper and lower substrate surfaces includes an array of conductor pads disposed thereon, each conductor pad in said array being electrically coupled to one of said metalized column extending through said substrate.

24. A multichip module stack system comprising:

a first multichip integrated circuit package and a second multichip integrated circuit package, each of said packages having an array of conductor pads on at least one of an upper surface and a lower surface thereof, each of said array of conductor pads being electrically connected to at least some of the integrated circuit chips disposed within said respective package, each of said packages including;

(i) a substrate,

(ii) a plurality of integrated circuit chips disposed on an upper surface of said substrate, said integrated circuit chips each having at least one interconnection pad on a top surface thereof,

(iii) an encapsulant surrounding said integrated circuit chips, said encapsulant having an upper surface above the tops of the integrated circuit chips and having a plurality of via openings therein, said openings being aligned with at least some of the interconnection pads,

(iv) a pattern of interconnection conductors disposed above the upper surface of said encapsulant so as to extend between at least some of the openings therein and so as to provide electrical connection between at least some of the interconnection pads through said via openings;

means for electrically coupling at least some of said conductor pads in said arrays of conductor pads on said first and second multichip packages; and

said packages being in a stacked configuration with said electrical coupling means located therebetween.

25. The multichip module stack system of claim 24, wherein each of said packages includes an array of conductor pads on a upper surface thereof and an array of conductor pads on a lower surface thereof.

26. The multichip modules stack system of claim 25, wherein said package electrical coupling means includes an array of button contacts, said button contact array being disposed between at least some of said arrays of contact pads of said stacked packages.

27. The multichip module stack system of claim 25, further comprising a plurality of multichip packages, each package being stacked within said stack system, and each being electrically coupled to an adjacent one of said packages of electrical connecting means disposed therebetween.

28. The multichip module stack system of claim 27, wherein each of said electrical connecting means includes an array of button contacts disposed between adjacent packages to engage at least some of said respective arrays of contact pads on the upper surface and the lower surface of said adjacent packages.

29. The multichip module stack system of claim 27, wherein each of said multichip packages disposed within said stack includes a physically engagable tab on an outer edge thereof.

30. The multichip module stack system of claim 29, further comprising at least one heat sink structure disposed within said stack.

31. The multichip module stack system of claim 30, wherein said heat sink structure includes:

a substrate having an upper surface and a lower surface, said upper and lower surfaces being in substantially parallel planes;

at least one liquid carrying cooling channel disposed within said substrate, said cooling channel extending substantially parallel to the planes of said upper and lower substrate surfaces; and

a plurality of vertically oriented metalized columns in said substrate, said columns being positioned so as not to intersect said at least one cooling channel and being oriented so as to substantially perpendicularly intersect the planes of said upper and lower surfaces.

34. A multichip integrated circuit package comprising:

a substrate having an upper and lower surface and at least one liquid receiving cooling channel therein, said cooling channel being disposed so as not to intersect said upper and lower substrate surfaces;

a plurality of integrated circuit chips disposed on said substrate'"'"'s upper surface, said integrated circuit chips each having at least one interconnection pad on a top surface thereof;

an encapsulant surrounding said integrated circuit chips, said encapsulant having an upper surface above the tops of the integrated circuit chips and having a plurality of via openings therein, said via openings being aligned with at least some of said interconnection pads; and

a pattern of interconnection conductors disposed above the upper surface of said encapsulant so as to extend between at least some of said openings and so as to provide electrical connection to at least some of said interconnection pads through said openings.

35. The integrated circuit package of claim 34, wherein said substrate includes a plurality of liquid cooling channels therein.

36. The integrated circuit package of claim 35, wherein each of said plurality of liquid cooling channels is disposed substantially parallel to said upper and lower surfaces of said substrate.

37. The integrated circuit package of claim 36, wherein the substrate comprises materials selected from the group consisting of glass, metal, ceramic, plastic, silicon and composites.

38. The integrated circuit package of claim 35, further comprising a patterned layer of thermal conductors disposed between said plurality of integrated circuit chips and said substrate'"'"'s upper surface, said thermal conductors being patterned to conduct heat from said integrated circuit chips to said substrate.

39. A heat sink structure for assembly with at least one multichip integrated circuit package, said structure comprising:

a substrate having an upper surface and a lower surface, said upper and lower surfaces being in substantially parallel planes;

at least one cooling channel disposed within said substrate, said at least one said cooling channel extending substantially parallel to the planes of said upper and lower substrate surfaces; and

at least one metalized column in said substrate, said metalized column being positioned so as not to intersect said at least one channel and being oriented as so to perpendicularly intersect the planes of said upper an lower surfaces.

40. The heat sink structure of claim 39, wherein a plurality of cooling channels is provided within said substrate, each of said channels being oriented substantially parallel to the planes of said upper and lower substrate surfaces.

41. The heat sink structure of claim 40, wherein a plurality of metalized columns is provided within said substrate.

45. A multichip module stack system comprising:

a first multichip integrated circuit package and a second multichip integrated circuit package, each of said packages having a plurality of columns therein extending between an upper surface and a lower surface thereof, and each including metallization disposed therein, at least some of said metalized columns being electrically connected to at least some of the integrated circuit chips disposed within said respective package, each of said packages including;

(i) a substrate,

(ii) a plurality of integrated circuit chips disposed on an upper surface of said substrate, said integrated circuit chips each having at least one interconnection pad on a top surface thereof,

(iii) an encapsulant surrounding said integrated circuit chips, said encapsulant having an upper surface above the tops of the integrated circuit chips and having a plurality of via openings therein, said via openings being aligned with at least some of the interconnection pads,

(iv) a pattern of interconnection conductors disposed above the upper surface of said encapsulant so as to extend between at least some of the openings therein and so as to provide electrical connection between at least some of the interconnection pads through said via openings;

means for electrically coupling at least some of said plurality of metalized columns of said first multichip package to at least some of said plurality of metalized columns of said second multichip package; and

said packages being disposed in a stacked configuration.

46. The multichip module stack system of claim 45, wherein said electrical coupling means includes a layer of metallization disposed so as to provide electrical connection between at least some of said metallized columns of said first multichip package with at least some of said metalized columns of said second multichip package.

47. The multichip module stack system of claim 45, wherein at least some of the substrates of said plurality of packages are sufficiently fine so as to be non-rigid, and said stack system further includes a rigid base plate upon which said plurality of packages are stacked.

48. The multichip module stack system of claim 45, wherein at least some of said plurality of metalized columns of said first multichip package align with at least some of said plurality of metalized columns o said second multichip package when said packages are disposed in said stacked configuration.

49. The multichip module stack system of claim 48, wherein said electrical coupling means of said stack includes a metallization layer disposed throughout the aligned columns of said stacked packages.