Programmable interface for computer system peripheral circuit card

• US 5,111,423 A
• Filed: 07/21/1988
• Issued: 05/05/1992
• Est. Priority Date: 07/21/1988
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Chan, Yiu-Fai, Hartmann, Robert F., Kopec, Stanley J. Jr.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Coleman, Eric
• Application Number:
  US07/222,565
• Time in Patent Office: 1,384 Days
• Field of Search: 364/200, 364/900, 365/230, 365/105, 307/406
• US Class Current: 710/9
• CPC Class Codes: G06F 12/0661 and decentralised selection

Abstract

A programmable interface for a peripheral circuit card is provided. The card is intended for use with a particular computer bus architecture, and the interface can be customized by a user for a particular card design. Instead of designing a custom interface chip, the designer can program one or more programmable logic devices on the interface chip to interface with whatever devices are on the peripheral circuit card.

Claims

1. A programmable interface for use in a peripheral circuit card in a computer system for interfacing between said peripheral circuit card and a communications bus in said computer system, said peripheral circuit card having configuration registers for receiving from said computer system via said communications bus various characteristics of said peripheral circuit card, said peripheral circuit card further having at least one application circuit chip thereon, said characteristics including an address pointer for said at least one chip, said programmable interface being capable of being programmed by a user prior to assembling said interface into said peripheral circuit card, said programmable interface comprising:

address input means for supplying address signals to said interface from said communications bus;

data input means for supplying data signals to said interface from said communications bus;

mask means for storing a plurality of alternate user-definable address ranges for each of said at least one application circuit chip, said mask means having mask output means and being an erasable programmable read-only memory capable of being programmed by a user prior to assembling said interface into said peripheral circuit card;

activation means programmable by a user prior to assembling said interface into said peripheral circuit card, said user-programmable activation means being a programmable logic array, for reading said address pointer from said configuration registers for activating that one of said plurality of address ranges stored in said programmable mask means which corresponds to said address pointer from said configuration registers;

comparator means having first and second inputs and an output, said mask output means being coupled to said first input of said comparator means;

means for applying said address signals to said second input of said comparator means; and

means connected to said output of said comparator means for generating an enable signal to enable said at least one application circuit chip to act on said data signals when said output of said comparator means indicates that said address signals match said mask;

whereby;

said programmable interface is capable of being programmed by programming said user-programmable mask means to store said at least one address range, thereby preparing said interface for assembling into said peripheral circuit card.

2. The programmable interface of claim 1 wherein said erasable programmable read-only memory is a CMOS erasable programmable read-only memory.

3. The programmable interface of claim 1 further comprising user-programmable latch means for, when an address signal is applied to said comparator means and said enable signal generating means generates an enable signal, latching said enable signal if desired by said user until another address signal is applied to said comparator means.

4. The programmable interface of claim 1 wherein:

said address signal comprises a number of bits;

said user-programmable mask means has a number of locations equal to said number of bits, each of said locations comprising two bits; and

each bit of said address signal and its complement are applied to said comparator means;

whereby;

said enable signal generating means can distinguish true, false and ignore for each of said bits.

5. The programmable interface of claim 1 wherein:

said peripheral circuit card comprises a plurality of application circuit chips; and

said programmable interface has one of said user-programmable mask means, one of said comparator means, one of said address signal applying means, and one of said enable signal generating means, for each of said plurality of application circuit chips.

6. The programmable interface of claim 1 wherein:

said peripheral circuit card comprises a plurality of application circuit chips; and

said programmable interface ha one of said user-programmable mask means, one of said comparator means, one of said address signal applying means, one of said enable signal generating means, and one of said programmable activation means for each of said plurality of application circuit chips.

7. The programmable interface of claim 1 further comprising feedback signal means for generating a feedback signal if at least one of said at least one enable signal generating means generates an enable signal.

8. The programmable interface of claim 7 further comprising feedback disabling means, programmable by a user prior to assembling said interface into said peripheral circuit card, for preventing, when so programmed by a user prior to assembling said interface into said peripheral circuit card, input to said feedback signal generating means of an enable signal generated by any desired one of said at least one enable signal generating means.

9. The programmable interface of claim 1 further comprising transfer means, programmable by a user prior to assembling said interface into said peripheral circuit card, for transferring data from said configuration registers to at least one of (a) other devices on said peripheral circuit card and (b) said communications bus.

10. The programmable interface of claim 9 wherein said user-programmable transfer means is a programmable crosspoint matrix.

11. The programmable interface of claim 9 further comprising feedback signal means for generating a feedback signal if at least one of said at least one enable signal generating means generates an enable signal.

12. The programmable interface of claim 11 further comprising feedback disabling means, programmable by a user to assembling said interface into said peripheral circuit card, for preventing, when so programmed by a user prior to assembling said interface into said peripheral circuit card, input to said feedback signal generating means of an enable signal generated by any desired one of said at least one enable signal generating means.

13. The programmable interface of claim 1 further comprising means for applying signals other than address signals to said address input means, wherein said mask means is capable of being programmed by a user, prior to assembling said interface into said peripheral circuit card, to decode said signals to perform other than addressing functions, whereby said other signals are decoded by said user-programmable mask means.

14. The programmable interface of claim 13 further comprising feedback signal means for generating a feedback signal if at least one of said at least one enable signal generating means generates an enable signal.

15. The programmable interface of claim 14 further comprising feedback disabling means, programmable by a user prior to assembling said interface into said peripheral circuit card, for preventing, when so programmed by a user prior to assembling said interface into said peripheral circuit card, input to said feedback signal generating means of at least one of (a) an enable signal generated as a result of application to said address input means of said other signals, and (b) an enable signal generated by any desired one of said at least one enable signal generating means.

16. The programmable interface of claim 1 wherein said computer provides said characteristics to said configuration registers based on identification data stored by said interface, said interface further comprising at least one user-programmable storage element for programmably storing said identification data.

17. The programmable interface of claim 16 wherein said user-programmable storage element comprises erasable programmable read-only memory.

18. The programmable interface of claim 17 wherein said user-programmable storage element comprises electrically erasable programmable read-only memory.

19. The programmable interface of claim 16 wherein said user-programmable storage element comprises fusible links.