Single event upset hardening CMOS memory circuit

• US 5,111,429 A
• Filed: 11/06/1990
• Issued: 05/05/1992
• Est. Priority Date: 11/06/1990
• Status: Expired due to Term

• Current Assignee: Idaho Research Foundation, Inc.
• Original Assignee: Idaho Research Foundation, Inc.
• Inventors: Whitaker, Sterling R.
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US07/609,583
• Time in Patent Office: 546 Days
• Field of Search: 365/154, 365/156, 365/190, 365/207, 365/208, 365/78
• US Class Current: 365/156
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/35606 with synchronous operation
• CPC Class Codes: H03K 3/356156 with synchronous operation
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A CMOS storage cell includes an n-channel storage circuit which has cross coupled n-channel storage transistors and a p-channel storage circuit including cross coupled p-channel storage transistors. Each of the n-channel storage transistors has an n-channel load transistor and each of the p-channel storage transistors has a p-channel load transistor. The n-channel load transistors are coupled to be controlled by the p-channel storage circuit and the p-channel load transistors are coupled to be controlled by the n-channel storage circuit. The n-channel load transistors are designed to carry less current than the p-channel storage transistors and the p-channel load transistors are designed to carry less current than the n-channel storage transistors. The storage cell can be used for a Static RAM or for a flip flop.

Claims

1. A cross coupled storage cell for a single binary bit of information comprising:

a) first cross coupled means for storing the bit;

b) second cross coupled means for storing the bit; and

c) means for cross coupling the first cross coupled means to the second cross coupled means.

2. The apparatus according to claim 1 wherein the first cross coupled means comprises all n-channel transistors and the second means comprises all p-channel transistors.

3. The apparatus according to claim 2 wherein each of the transistors has a source, a drain and a gate

a) wherein the first cross coupled means comprises:

1) a first n-channel storage node and a second n-channel storage node;

2) a first n-channel storage transistor having its drain coupled to the first n-channel storage node and its source couple to a ground potential;

3) a second n-channel storage transistor having its drain coupled to the first n-channel storage node and its source coupled to the ground potential;

4) a first n-channel load transistor having its drain coupled to a power supply potential and its source coupled to the first n-channel storage node; and

5) a second n-channel load transistor having its drain coupled to the power supply potential and its source coupled to the second n-channel storage node;

6) the gate of the first n-channel storage transistor is coupled to the second n-channel storage node; and

7) the gate of the second n-channel transistor is coupled to the first n-channel storage node;

b) wherein the second cross coupled means comprises;

1) a first p-channel storage node and a second p-channel storage node;

2) a first p-channel storage transistor having its source coupled to the first storage node and its drain coupled to the power supply potential;

3) a second p-channel storage transistor having its source coupled to the first storage node and its drain coupled to the power supply potential;

4) a first p-channel load transistor having its source coupled to the ground supply potential and its drain coupled to the first p-channel storage node; and

5) a second p-channel load transistor having its source coupled to the ground potential and its drain source coupled to the second p-channel storage node;

6) the gate of the first n-channel storage transistor is coupled to the second n-channel storage node; and

7) the gate of the second n-channel transistor is coupled to the first n-channel storage node; and

c) wherein the means for cross coupling the first cross coupled means to the second cross coupled means comprises;

1) the gate of the first n-channel load transistor is coupled to the first p-channel storage node;

2) the gate of the second n-channel load transistor is coupled to the second p-channel storage node;

3) the gate of the first p-channel load transistor is coupled to the first n-channel storage node; and

4) the gate of the second p-channel load transistor is coupled to the second n-channel storage node.

4. The apparatus according to claim 3 wherein the p-channel load transistors are designed to carry less current than the n-channel storage transistors and the n-channel load transistors are designed to carry less current than the p-channel storage transistors.

5. The apparatus according to claim 4 wherein the storage cell is for a Static RAM.

6. The apparatus according to claim 4 wherein the storage cell is for a flip flop.

7. A CMOS storage cell comprising:

a) an n-channel storage circuit including cross coupled n-channel storage transistors each having an n-channel load transistor; and

b) a p-channel storage circuit including cross coupled p-channel storage transistors each having an n-channel load transistor, wherein the n-channel load transistors are coupled to be controlled by the p-channel storage circuit and the p-channel load transistors are coupled to be controlled by the n-channel storage circuit.

8. The apparatus according to claim 7 wherein the n-channel load transistors are designed to carry less current than the p-channel storage transistors and the p-channel load transistors are designed to carry less current than the n-channel storage transistors.

9. The apparatus according to claim 8 wherein the storage cell is for a Static RAM.

10. The apparatus according to claim 8 wherein the storage cell is for a flip flop.