Integrated circuit device particularly adapted for high voltage applications

• US 5,113,236 A
• Filed: 12/14/1990
• Issued: 05/12/1992
• Est. Priority Date: 12/14/1990
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: North American Philips Corp. (Koninklijke Philips N.V.)
• Inventors: Merchant, Steven L., Shackle, Peter W., Arnold, Emil
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): RUSSELL, DANIEL
• Application Number:
  US07/628,307
• Time in Patent Office: 515 Days
• Field of Search: 357/42, 357/23.4, 357/68, 357/71, 357/41, 357/23
• US Class Current: 257/347
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76267 Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical

Abstract

A silicon on insulator of integrated circuit comprising a plurality of components typically adopted for high voltage application having a semiconductor substrate of a first conductivity type, an insulating layer provided on the substrate, a semiconductor layer provided on the insulating layer, a number of laterally separated circuit elements forming parts of a number of subcircuits provided in the semiconductor layer, a diffusion layer of a second conductivity type opposite to that of the first conductivity type provided in the substrate and laterally separated from all the other circuit elements and means for holding the diffusion layer at a voltage at least equal to that of the highest potential of any of the subcircuits present in the integrated device.

Claims

1. An integrated circuit device exhibiting improved voltage breakdown properties, comprising a semiconductor foundational substrate of a resistivity greater than about 100 ohm-cm of a first conductivity type, an insulating layer provided on said substrate, a semiconductor layer provided on said insulating layer, a plurality of laterally separated circuit elements forming parts of subcircuits provided in said semiconductor layer, a diffusion area of a second conductivity type, opposite to said first conductivity type, provided in said substrate, underlying none of said circuit elements and means for contacting and holding said diffusion area at a voltage at least equal to the highest potential of any subcircuit in said circuit device.

2. The integrated circuit device of claim 1, wherein said substrate is a p-type semiconductor substrate and said diffusion area is a n-type diffusion area.

3. The integrated circuit device of claim 2, wherein the substrate is a p-type silicon substrate and the insulating layer is silicon dioxide.

4. The integrated circuit device of claim 3 wherein the semiconducting layer is substantially n-type monocrystalline silicon layer.

5. The integrated circuit device of claim 3, wherein a single diffusion area is provided for a multiplicity of circuit components.

6. The integrated circuit device of claim 3 wherein the diffusion layer is held at a voltage higher than the highest potential of any subcircuit in said integrated circuit device and said diffusion area is provided with a separate potential source.

7. An integrated circuit device exhibiting improved voltage breakdown properties, particularly adapted for high voltage applications, comprising a relatively high resistivity semiconductor foundational substrate of a first conductivity type, an insulating layer provided on said substrate, a semiconductor layer of a second conductivity type opposite to said first conductivity type provided on said insulating layer, a plurality of circuit elements forming parts of subcircuits provided in said semiconductor layer, a diffusion area of said second conductivity type provided in said semiconductor layer, underlying none of said circuit elements, said diffusion area having no overlying circuit element, and means for holding said diffusion area at a voltage at least equal to the highest potential of any subcircuit in said circuit device.

8. The integrated circuit device of claim 7 wherein the substrate is a p-type semiconductor substrate, the semiconductor layer is an n-type semiconductor layer, and the diffusion area is an n-type diffusion area.

9. The integrated circuit device of claim 8 wherein the substrate is a p-type silicon substrate, the insulating layer is silicon dioxide and the semiconductor layer is substantially n-type monocrystalline silicon layer.

10. An integrated circuit device of claim 9 wherein the diffusion area is held at a voltage higher than the highest potential of any subcircuit in said integrated circuit device and said diffusion area provided with a separate potential source.

11. A semiconductor-on-insulator lateral MOS transistor source-follower bridge structure exhibiting improved voltage breakdown properties, particularly adapted for high voltage applications comprising a semiconductor foundational substrate of a first conductivity type, an insulating layer provided on said substrate, a semiconducting layer provided on said insulating layer, drain, gate, source and interconnect portions of said transistor provided in said semiconductor layer, a diffusion area of a second conductivity type, opposite to said first conductivity type, provided in said substrate, underlying none of said drain, gate and source portions and means for holding said diffusion area at a voltage at least equal to the highest potential of said drain and source portions.

12. The structure of claim 11 wherein said substrate is a p-type semiconductor substrate and said diffusion area is a n-type diffusion area.

13. The structure of claim 12 wherein the substrate is p-type silicon substrate and the insulating layer is silicon dioxide.

14. The structure of claim 13 wherein the semiconductor layer is substantially n-type monocrystalline silicon layer.