Communication apparatus for reassembling packets received from network into message

• US 5,113,392 A
• Filed: 06/18/1990
• Issued: 05/12/1992
• Est. Priority Date: 06/19/1989
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd., Hitachi Microcomputer Engineering Limited
• Original Assignee: Hitachi, Ltd., Hitachi Microcomputer Engineering Limited
• Inventors: Kobayashi, Naoya, Hirayama, Satoru, Iiyama, Tatsuhito, Nakamura, Kazunori, Takada, Osamu, Amada, Eiichi, Takiyasu, Yoshihiro, Jusa, Hidehiko, Yamaga, Mitsuhiro
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Marcelo, Melvin
• Application Number:
  US07/539,961
• Time in Patent Office: 694 Days
• Field of Search: 370/60, 370/61, 370/94.1, 370/99, 370/85.15
• US Class Current: 370/473
• CPC Class Codes: H04L 49/252 Store and forward routing
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags

Abstract

In a network having a plurality of node apparatus connected to a transmission line, each node apparatus segmenting a transmission message into information blocks of a predetermined length and transmitting them to the transmission line in the form of a fixed length packet (cell) having a source address, each node apparatus sequentially stores packets having different source addresses in vacant memory blocks of a buffer memory. There is written in each memory block the packet data as well as a next address pointer indicating a memory block in which the next received packet having the same source address is stored. When a packet containing the last information block of a message is received, stored in a read address queue is the address indicating the memory block which stores the first information block of the same packet. Reading the first block of a message from the buffer memory is executed in accordance with an address read from the read address queue, and reading the following blocks is executed in accordance with the next address pointer. Read/write of the buffer memory is alternately executed in units of memory block.

Claims

1. A communication apparatus for receiving a plurality of fixed length packets transmitted from a plurality of transmission source apparatus, and reassembling a communication message from a plurality of packets having the same transmission source address, each packet having a header field including a transmission source address and a message information field including an information block obtained by segmenting a message, comprising:

a buffer memory divided into a plurality of memory blocks for storing packet data;

first memory means for storing addresses each indicating a vacant memory block within said buffer memory;

second memory means for storing next address pointers correspondingly with each transmission source address, each next address pointer indicating a memory block in which the data of a packet to be received next are stored;

third memory means for storing addresses correspondingly with each transmission source address, each address indicating a memory block in which the packet data including the first information block of a message are stored;

fourth memory means for storing addresses correspondingly with each transmission source address, each address indicating a memory block stored in which are the packet data including the first information block of a message allowed to be reassembled;

write control means which operates such that when there is received a packet including the first information block of a message transmitted upon segmentation into a plurality of information blocks, an address read from said first memory means is stored in said third memory means, the data of said received packet are stored in a vacant memory block indicated by said address, and another address read from said first memory means is stored in said second memory means and in said memory block storing said packet data; and

that when there is received a packet including one of the second and following information blocks of said message, the data of said received packet are stored in a memory block indicated by an address read from said second memory means, if said received packet does not include the last information block of said message, an address read from said first memory means is stored in said second memory means and in said memory block storing the data of said received packet, and if said received packet includes the last information block of said message, an address read from said third memory means is stored in said fourth memory means; and

read control means which operates such that the first information block of a message is read from the memory block indicated by an address read from said fourth memory means, and the second and following information blocks of said message are sequentially read in accordance with next address pointers read from respective memory blocks.

2. A communication apparatus according to claim 1, wherein said write and read control means alternately access said buffer memory at a predetermined operation cycle, and the packet data of one memory block are processed at each operation cycle.

3. A communication apparatus according to claim 1, further comprising means for extracting said message information field from each received packet, whereby the contents of said message information field are stored as said packet data in each memory block of said buffer memory.

4. A communication apparatus according to claim 1, wherein said write control means includes means for storing, when a received packet includes all information of a message, an address read from said first memory means directly, or via said third memory, in said fourth memory means, and storing the data of said received packet in a memory block indicated by said address.

5. A communication apparatus for receiving a plurality of fixed length packets transmitted from a plurality of transmission source apparatus, and reassembling a communication message from a plurality of packets having the same transmission source address, each packet having a header field including a transmission source address, a message information field including an information block obtained by segmenting a message and a code field for indicating the position of an information block within a message, comprising:

a buffer memory divided into a plurality of memory blocks for storing packet data;

first memory means for storing addresses each indicating a vacant memory block within said buffer memory;

second memory means for storing addresses correspondingly with each transmission source address, each address indicating a memory block storing the data of a preceding packet;

third memory means for storing addresses correspondingly with each transmission source address, each address indicating a memory block in which the packet data including the first information block of a message are stored;

fourth memory means for storing addresses correspondingly with each transmission source address, each address indicating a memory block stored in which are the packet data including the first information block of a message allowed to be reassembled;

write control means which operates such that when there is received a packet including the first information block of a message transmitted upon segmentation into a plurality of information blocks, an address read from said first memory means is stored in said second and third memory means, and the data of said received packet are stored in a vacant memory block indicated by said address; and

that when there is received a packet including one of the second and following information blocks of said message, the data of said received packet are stored in a ,memory block indicated by an address read from said first memory means, and said address is stored as a next address pointer in a memory block at a predetermined memory area indicated by an address read from said second means, and if said received packet includes the last information block of said message, an address read from said third memory means is stored in said fourth memory means; and

read control means which operates such that the first information block of a message is read from the memory block indicated by an address read from said fourth memory means, and the second and following information blocks of said message are sequentially read in accordance with next address pointers read from respective memory blocks.

6. A communication apparatus according to claim 5, wherein said write control means includes means for adding a constant value to an address read from said first memory means, whereby when there is received a packet including the first information block of a message, an address outputted from said adding means is stored in said second memory, and when there is received one of the second and following information blocks of said message, said address as a next address pointer is stored in said buffer memory at the location indicated by an address read from said second memory means.

7. A communication apparatus according to claim 5, wherein said write and read control means alternately access said buffer memory at a predetermined operation cycle, and the packet data of one memory block are processed at each operation cycle.

8. A communication apparatus according to claim 5, wherein each memory block stores at least the contents of said message information field and position code field included in a received packet, and said read control means discriminates the last information block of a message in accordance with said position code read from each memory block.