Predistortion arrangement for a digital transmission system
First Claim
1. A predistortion arrangement for a digital transmission system which transmits complex input data at a rate defined by a clock having a period T, comprising a power amplifier which introduces nonlinear distortion into data signals being transmitted, a modulator driving the power amplifier, and a predistortion circuit for predistorting input data signals in a sense opposite to distortion introduced in the power amplifier, and providing the predistorted signals to the modulator,characterized in that the predistortion circuit comprises a transmit filter means, responsive to receiving input data, for providing in-phase and quadrature channels of filtered, oversampled data encoded with 2N bits (N bits per channel), at a rate k/T, where k is an integer greater than 1,encoder means for receiving said filtered, oversampled data, and transforming the filtered data encoded with 2N bits into data encoded with 2M bits, where M<
- N,a memory addressed by the 2M bits, for storing 22M complex predistortion coefficients,a complex multiplier, for multiplying the 2N bits of each data element by a selected predistortion coefficient, to produce predistorted input data (FI, FQ).
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Accused Products
Abstract
A predistortion arrangement (9) for a digital transmission system transmits complex input data of a constellation by means of a modulator (14) and a power amplifier (15) which distorts the data. The arrangement comprising a predistortion circuit (11) which predistorts the input data in opposite sense before they pass through the amplifier and a transmit filter (10) which applies oversampled filtered data encoded with 2N bits to the predistortion circuit (11) at the rate k/T. The predistortion circuit (11) is formed from an encoder (20) transforming the filtered 2N-bit encoded data into data encoded with 2M bits (M<N) which address a memory (51) that stores complex predistortion coefficients, and a complex multiplier (52) that multiplies for each data element the 2N bits of the filtered data element by the selected predistortion coefficient for producing predistorted data.
78 Citations
12 Claims
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1. A predistortion arrangement for a digital transmission system which transmits complex input data at a rate defined by a clock having a period T, comprising a power amplifier which introduces nonlinear distortion into data signals being transmitted, a modulator driving the power amplifier, and a predistortion circuit for predistorting input data signals in a sense opposite to distortion introduced in the power amplifier, and providing the predistorted signals to the modulator,
characterized in that the predistortion circuit comprises a transmit filter means, responsive to receiving input data, for providing in-phase and quadrature channels of filtered, oversampled data encoded with 2N bits (N bits per channel), at a rate k/T, where k is an integer greater than 1, encoder means for receiving said filtered, oversampled data, and transforming the filtered data encoded with 2N bits into data encoded with 2M bits, where M< - N,
a memory addressed by the 2M bits, for storing 22M complex predistortion coefficients, a complex multiplier, for multiplying the 2N bits of each data element by a selected predistortion coefficient, to produce predistorted input data (FI, FQ). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
- N,
Specification