System for dynamically providing predicted high/slow speed accessing memory to a processing unit based on instructions
First Claim
1. A system for predicting processing unit memory addressing and for selectively providing high speed addressing of a random access memory, the system comprising;
- a processing unit;
a random access memory connected to supply data and instructions to said processing unit in response to memory accesses from the processing unit, said random access memory being operable in a high speed mode for predetermined sequences of addresses and otherwise operable in a low speed mode;
predicting means coupled to said random access memory for receiving instructions supplied by said random access memory to said processing unit and for providing a first signal in response to received instructions if the next memory access by said processing unit is to an address accessible in the high speed mode; and
means for accessing said random access memory in the high speed mode in response to the first signal, and in the low speed mode otherwise.
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0 Petitions
Accused Products
Abstract
A system (60) for predicting CPU addresses includes a CPU (34) connected by bus (62) to page mode address predicting circuit (64). The page mode address predicting circuit (64) is connected to memory arbitration circuits (66) by bus (68). The memory arbitration circuits (66) are connected to RAM (42) by address, data and control busses (44), (46) and (48). The CPU (34), page mode address predicting circuit (64) and the memory arbitration circuits 66 are contained in a microprocessor integrated circuit (32). The page mode predicting circuit 64 examines signals from the CPU (34) to be supplied to the data bus (46) at the time of a SYNC pulse. This operation results in examination of the first byte of a CPU instruction to determine how many of the following memory accesses will be able to be carried out in high speed mode. If it is determined that the next memory access will be able to be carried out in the high speed mode, then the next memory cycle is performed using a high speed access mode of the RAM (42), e.g. page mode access.
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Citations
15 Claims
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1. A system for predicting processing unit memory addressing and for selectively providing high speed addressing of a random access memory, the system comprising;
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a processing unit; a random access memory connected to supply data and instructions to said processing unit in response to memory accesses from the processing unit, said random access memory being operable in a high speed mode for predetermined sequences of addresses and otherwise operable in a low speed mode;
predicting means coupled to said random access memory for receiving instructions supplied by said random access memory to said processing unit and for providing a first signal in response to received instructions if the next memory access by said processing unit is to an address accessible in the high speed mode; andmeans for accessing said random access memory in the high speed mode in response to the first signal, and in the low speed mode otherwise. - View Dependent Claims (2, 3, 4)
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5. A method for dynamically providing selective high speed memory addressing in a system having a processing unit and a random access memory connected to supply instructions to the processing unit, the random access memory being operable in a high speed mode for predetermined sequences of addresses and otherwise operable in a low speed mode, the method comprising the steps of:
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providing instructions from the random access memory to the processing unit; predicting from the provided instructions if a subsequent memory access is to an address accessible in the high speed mode; and addressing said random access memory in the high speed mode in response to a prediction and in the low speed mode otherwise. - View Dependent Claims (6, 7, 8, 9)
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10. A system for dynamically providing selective high speed memory addressing, the system comprising;
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a processing unit; a random access memory connected to supply instructions to said processing unit in response to memory accesses from said processing unit, said random access memory being operable in a high speed mode for predetermined sequences of addresses and otherwise operable in a low speed mode; predicting means coupled to receive instructions supplied to said processing unit for providing a first signal in response to received instructions if the next memory access is to an address that accessible in the high speed mode; and mode selection means for accessing said random access memory in the high speed mode in response to the first signal and in the low speed mode otherwise. - View Dependent Claims (11, 12, 13, 14, 15)
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Specification