Triple comparator circuit

• US 5,115,151 A
• Filed: 06/08/1990
• Issued: 05/19/1992
• Est. Priority Date: 06/08/1990
• Status: Expired due to Term

• Current Assignee: Western Digital Corporation
• Original Assignee: Western Digital Corporation
• Inventors: Hull, Richard W., O'Shaughnessy, Timothy G.
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US07/535,177
• Time in Patent Office: 711 Days
• Field of Search: 307/350, 307/355, 307/362, 307/494, 307/559, 307/565, 307/568
• US Class Current: 327/65
• CPC Class Codes: G01R 19/0038 Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing pulses or pulse trains according to amplitude)
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

A comparator which is used to compare two analog voltages and provide a single ended output comprises three CMOS differential amplifiers. The use of three differential amplifiers provides improved matching of input capacitance, and a reduction in propagation delay over prior art use of a single differential amplifier. The comparator may be adopted for use in certain CMOS processes to extend the maximum operating voltage by limiting the internal node voltages otherwise subject to damage from impact ionization. An alternative embodiment is disclosed for comparing two analog voltages that are outside the power supply voltage range.

Claims

1. A high impedance differential comparator circuit having symmetrical delay comprising;

a first MOS differential amplifier having a first input, a second input and an output, the first input connected to a first signal source and the second input connected to second signal source;

a second MOS differential amplifier identical to the first differential amplifier having the first input connected to the second signal source and the second input connected to the first signal source;

a third MOS differential amplifier having a first input connected to the output of the first differential amplifier, a second input connected to the output of the second differential amplifier and an output; and

,

means for clamping the outputs of the first and second differential amplifiers thereby providing a maximum limit on voltage at the first and second inputs to the third differential amplifier.

2. A high impedance differential comparator circuit having symmetrical delay comprising:

first and second current source biased MOS differential amplifiers with active current mirror loads, each amplifier having a first input, a second input, and an output, the first input of the first amplifier and the second input of the second amplifier connected to a first signal source and the second input of the first amplifier and the first input of the second amplifier connected to a second signal source;

a third current source biased MOS differential amplifier having an active current mirror load and having a first input connected to the output of the first amplifier and a second input connected to the output of the second amplifier and an output;

a first diode connected MOS device drain connected intermediate the output of the first amplifier and the first input of the third amplifier;

a second diode connected MOS device drain connected intermediate the output of the second amplifier and the second input of the third amplifier; and

,

a MOS invertor stage connected to the output of the third amplifier.

3. A comparator circuit as defined in claim 2 further comprising means for biasing the current sources of the first and second amplifiers and means for biasing the current source of the third amplifier.

4. A differential comparator circuit as defined in claim 3 further comprising a first voltage supply connected to the current sources of the first and second amplifiers and a second voltage supply connected to the current source of the third amplifier and the MOS invertor stage.