Anti-aliasing dithering method and apparatus for low frequency signal sampling
First Claim
1. A method for sampling an analog input signal and storing digital representation of said samples in a memory, said method comprising:
- generating a series of clock pulses at a predetermined frequency Fo ;
sampling said input signal at each clock pulse and converting said sample to a predetermined digital format;
arbitrarily selecting one of said clock pulses from each successive series of N clock pulses (where N is a predetermined integer much greater than one) by means of the following sequence of steps for each series of N clock pulses;
(a) generating an arbitrary target integer between zero and N - 1 and loading a counter with a digital value equal to N - 1 at the first clock pulse in each series of N clock pulses, where said target integer is typically not equal to the target integer for the previous series of N clock pulses;
(b) decrementing said counter by one at each of the next N clock pulses; and
(c) comparing said counter with said target integer at each clock pulse and selecting the clock pulse for which said counter equals said target integer; and
storing the current sample in a memory at each of said selected clock pulses.
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Abstract
A method and apparatus is disclosed to prevent aliasing while sampling a low frequency analog input signal. A clock produces a series of electrical pulses at a predetermined frequency Fo. An analog-to-digital ("A/D") converter samples the input signal at each clock pulse. Sample selection means randomly select one clock pulse from each successive series of N clock pulses, where N is a predetermined integer much greater than one. A memory receives the digital output values from the A/D converter, but only stores the current digital output value at each selected clock pulse. As a result, the long-term average frequency of sample storage is substantially equal to Fo /N, but the interval between successive samples is random (i.e. the interval between successive samples is typically not equal to N clock pulses).
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Citations
11 Claims
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1. A method for sampling an analog input signal and storing digital representation of said samples in a memory, said method comprising:
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generating a series of clock pulses at a predetermined frequency Fo ; sampling said input signal at each clock pulse and converting said sample to a predetermined digital format; arbitrarily selecting one of said clock pulses from each successive series of N clock pulses (where N is a predetermined integer much greater than one) by means of the following sequence of steps for each series of N clock pulses; (a) generating an arbitrary target integer between zero and N - 1 and loading a counter with a digital value equal to N - 1 at the first clock pulse in each series of N clock pulses, where said target integer is typically not equal to the target integer for the previous series of N clock pulses; (b) decrementing said counter by one at each of the next N clock pulses; and (c) comparing said counter with said target integer at each clock pulse and selecting the clock pulse for which said counter equals said target integer; and storing the current sample in a memory at each of said selected clock pulses.
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2. In an oscilloscope adapted to sample an analog input signal, store digital values representative of said samples in a memory, and display a visual representation of said input signal by plotting said stored values along a predetermined axis, a method of sampling and storing said samples comprising:
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generating a series of clock pulses having a predetermined frequency Fo ; sampling said analog input signal at each clock pulse and converting each of said samples to a predetermined digital format suitable for storage in said memory; randomly selecting one of said clock pulses from each successive series of N clock pulses, where N is an integer much greater than one, by means of the following sequences of steps for each series of N clock pulses; (a) generating a random integer between zero and N - 1 and loading a counter with a digital value equal to N - 1 at the first clock pulse in each series of N clock pulses; (b) decrementing said counter by one at each of the next N clock pulses; and (c) comparing said counter with said random integer at each clock pulse and selecting the clock pulse for which said counter equals said random integer; storing the current sample in a memory at each of said selected clock pulses; and displaying said stored samples in said visual representation after a predetermined number of samples have been stored in said memory.
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3. An oscilloscope adapted to sample an analog input signal, store digital values representative of said samples in a memory, and display a visual representation of said input signal by plotting said stored values along a predetermined axis, said oscilloscope comprising:
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a clock producing a series of electrical pulses at a predetermined frequency; an analog-to-digital ("A/D") converter adapted to sample said analong input signal and produce a digital output value that is a digital representation of said analog input signal at each of said clock pulses; a memory adapted to receive said digital output value from said A/D converter, and to store said digital output value when triggered by a control signal; sample selection means having; (a) a 1-in-N block adapted to count said clock pulses and produce one output pulse for each series of N clock pulses; (b) a random number generator adapted to generate a random digital value between zero and N - 1, said random value changing after each output pulse from said 1-in-N block; and (c) a decrementer adapted to load said random value from said random number generator in response to each output pulse from said 1-in-N block, thereafter progressively decrement said random value for each clock pulse, and trigger said memory when said decremented random value reaches zero; and display means adapted to create said visual representation of said stored samples after a predetermined number of samples have been stored in said memory. - View Dependent Claims (4, 5)
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6. An apparatus for sampling an analog input signal and storing digital representations of said samples, said apparatus comprising:
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a clock producing a series of electrical pulses at a predetermined frequency, Fo ; an analog-to-digital ("A/D") converter adapted to sample said analog input signal and produce a digital output value in response to each of said clock pulses that is a digital representation of said analog input signal; a memory adapted to receive said digital output value from said A/D converter and to store a plurality of said digital output value, said memory storing the current digital output value from said A/D converter when triggered by a control signal; and sample selection means having; (a) a 1-in-N block adapted to count said clock pulses and produce one output pulse for each series of N clock pulses; (b) a random number generator adapted to generate a random digital value between zero and N - 1, said random value changing after each output pulse from said 1-in-N block; and (c) a decrementer adapted to load said random value from said random number generator in response to each output pulse from said 1-in-N block, thereafter progressively decrement said random value for each clock pulse, and trigger said memory when said decremented random value reaches zero. - View Dependent Claims (7)
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8. An apparatus for sampling an analog input signal and storing digital representation of said samples, said apparatus comprising:
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a clock producing a series of electrical pulses at a predetermined frequency, Fo ; an analog-to-digital ("A/D") converter adapted to sample said analog input signal and produce a digital output value in response to each of said clock pulses that is a digital representation of said analog input signal; a memory adapted to receive said digital output values from said A/D converter and to store a plurality of said digital output values, said memory storing the current digital output value from said A/D converter when triggered by a control signal; and sample selection means having; (a) a decrementer adapted to receive said clock pulses, having a counter adapted to decrement from a digital value of N - 1 to zero for each successive series of N clock pulses (where N is a predetermined integer much greater than one); (b) a random number generator adapted to generate a random digital value between zero and N - 1, said random value changing once for each of said series of N clock pulses; and (c) an equality detector adapted to trigger said memory when said random value equals the value of said decrementer counter. - View Dependent Claims (9)
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10. An apparatus for sampling an analog input signal and storing digital representations of said samples, said apparatus comprising:
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a clock producing a series of electrical pulses at a predetermined frequency, Fo ; an analog-to-digital ("A/D") converter adapted to sample said analog input signal and produce a digital output value in response to each of said clock pulses that is a digital representation of said analog input signal; a memory adapted to receive said digital output values from said A/D converter and to store a plurality of said digital output values, said memory storing the current digital output value from said A/D converter when triggered by a control signal; and sample selection means having; (a) a first decrementer adapted to receive said clock pulses, having a counter adapted to progressively decrement from a digital value of N - 1 to zero for each series of N clock pulses (where N is a predetermined integer greater than one), and to produce an output pulse when said counter reaches zero; (b) a random number generator adapted to generate a random digital value between zero and N - 1, said random value changing after each output pulse from said first decrementer; and (c) a second decrementer adapted to receive said clock pulses, and having a counter adapted to load said random value from said random number generator in response to each output pulse from said first decrementer;
said second decrementer thereafter progressively decrementing said random value for each clock pulse, and triggering said memory when said counter reaches zero. - View Dependent Claims (11)
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Specification