MOS type semiconductor device and method for manufacturing the same

• US 5,115,290 A
• Filed: 09/05/1990
• Issued: 05/19/1992
• Est. Priority Date: 09/06/1989
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Murakami, Kouji, Matsunaga, Taira
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Dang, Hung Xuan
• Application Number:
  US07/577,749
• Time in Patent Office: 622 Days
• Field of Search: 357/23.4, 357/715, 357/71, 357/675, 357/67, 357/23.9, 357/23.3, 437/192, 437/200, 437/40, 437/41
• US Class Current: 257/388
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A MOS type semiconductor device and a method for the manufacture of the same are disclosed in which a gate electrode is so formed over a semiconductor substrate of a first conductivity type with a gate insulating film formed therebetween as to provide a three-layered structure composed of a first high melting point metal silicide layer formed on the gate insulating film, high melting point metal layer formed on the first high melting point metal silicide and a second high melting point metal silicide layer formed on the high melting point metal layer. In the gate electrode, a length of the first high melting point silicide layer defined in the same direction as that in which a channel region extends is made smaller in length than the high melting point metal layer.

Claims

1. A MOS type semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

source and drain regions of a second conductivity type formed in a surface portion of the semiconductor substrate;

a channel region formed in the surface portion of the semiconductor substrate such that it extends between the source and drain regions;

a gate insulating film formed at least on the channel region; and

a gate electrode comprising a first high melting point metal silicide layer formed on the gate insulating film, a high melting point metal layer formed on the first high melting point metal silicide layer and a second high melting point metal silicide layer formed on the high melting point metal layer, in which a length of the first high melting point silicide layer defined in the same direction as that in which the channel region extends is made shorter in length than the high melting point metal layer.

2. The MOS type semiconductor device according to claim 1, wherein said first and second high melting point silicide layers are one selected from the group consisting of a molybdenum silicide layer, a titanium silicide layer and tungsten silicide layer and said high melting point metal layer is formed of a material selected from the group consisting of molybdenum, titanium and tungsten.