Method and apparatus for bus executed boundary scanning

• US 5,115,435 A
• Filed: 10/19/1989
• Issued: 05/19/1992
• Est. Priority Date: 10/19/1989
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: NCR Corporation
• Inventors: Bullinger, Philip W., Langford, Thomas L. II
• Primary Examiner(s): Ruggiero, Joseph
• Assistant Examiner(s): HUA, LY
• Application Number:
  US07/423,924
• Time in Patent Office: 943 Days
• Field of Search: 371/22.3, 371/25.1, 371/22.1
• US Class Current: 714/727
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test
• CPC Class Codes: G01R 31/318572 Input/Output interfaces

Abstract

A boundary scan test circuit for inclusion into ASIC and or VLSI circuits which does not require any additional pads/pins to support full boundary scan functionality. The invention uses the power and capability of existing address and data buses to transfer test data into the integrated circuit under boundary scan test, and uses the same buses to transfer test results out of the integrated circuit under test to be interpreted by the test processor of the system.

Claims

1. A boundary scan test apparatus for use in a digital integrated circuit of a digital system, the digital integrated circuit having an integrated circuit data bus that connects to an external system data bus, a normal mode of operation and a boundary scan test mode of operation, said boundary scan test apparatus, comprising:

means for switching a plurality of data inputs and a plurality of data outputs of the digital integrated circuit from the normal mode of operation to the boundary scan test mode of operation to form a boundary scan test circuit;

means for inputting a boundary scan test word from the external system data bus via the integrated circuit data bus to the boundary scan test circuit as a test input thereto; and

means for outputting a boundary scan test response to the boundary scan test word, from the boundary scan test circuit via the integrated circuit data bus to the external system data bus;

whereby the boundary scan test apparatus boundary scan tests the digital integrated circuit without adding any external lead connections beyond those used by the integrated circuit during the normal mode of operation.

2. For use in a digital integrated circuit having a plurality of boundary scan data inputs, a plurality of boundary scan data outputs, and a parallel data bus;

a test apparatus comprising;

means for receiving a control word from the parallel data bus and outputting a select signal in response to said control word;

means for selecting a boundary scan test circuit in response to said select signal, said boundary scan test circuit selecting means is connected to the plurality of boundary scan inputs and outputs;

means for receiving a scan data test word from the parallel data bus;

means for communicating the scan data test word into the plurality of boundary scan inputs and outputs of the boundary scan test circuit; and

means for receiving a scan data test response word from a portion of the digital integrated circuit under test in response to the scan data test word from the boundary scan test circuit.

3. The test apparatus according to claim 2, wherein if said boundary scan circuit is selected, a plurality of normal mode connections between a plurality of input pad receivers and core logic circuits of the integrated circuit are disconnected.

4. A bus executed boundary scan apparatus, for use in a digital integrated circuit having an address decoder and a data bus, comprising:

a control register connected to the data bus for receiving a boundary scan control word;

scan clock means for generating a scan clock signal in response to a write instruction to a preselected address decoded by the decoder;

scan data input register means connected to the data bus for receiving a scan data word therefrom;

the scan data input register means having a shifted serial output responsive to said scan clock signal for outputting said scan data word as a sequence of serial bits;

scan path connection means connected to said scan data input register means and responsive to said boundary scan control word for logically connecting a scan path communicating said sequence of serial bits to an output thereof;

assembling means connected to said output of said scan path connection means for assembling said sequence of serial bits into a scan test word for testing a portion of the integrated circuit;

means connected to said assembling means for scanning said scan test word into said portion of the integrated circuit;

output means connected to said portion of the integrated circuit for receiving a test response to said scan test word therefrom; and

output register means connected to said output means for storing said test response and transmitting said test response to the data bus.

5. The test circuit set forth in claim 4, wherein said output means is connected to said output register means by a multi-conductor bus which connects a plurality of monitor bits within said test response to a plurality of storage locations within said output register means for storing said test response therein in a parallel data transfer.

6. The test circuit set forth in claim 4, wherein said output means is connected to said output register means by a single-conductor bus which serially transfers said test response to a plurality of storage locations within said output register means for storing said test response therein.

7. For use in a digital integrated circuit having a parallel bus which transfers multiplexed address words and a data words, a test circuit comprising:

a control register connected to said parallel bus and for receiving a scan path control word;

scan clock means connected to said parallel bus for generating a scan clock signal in response to a write instruction to a preselected address word;

scan data input register means connected to said parallel bus for receiving a scan data word therefrom;

said scan data input register having a shifted serial output responsive to said scan clock signal for outputting said scan data word as a sequence of serial bits;

scan path connection means connected to said scan data register means and responsive to said scan path control word for logically connecting a scan path that communicates said sequence of serial bits to an output thereof;

assembling means connected to said output of said scan path connection means for assembling said sequence of serial bits into a scan test word for testing a portion of the integrated circuit;

means connected to said assembling means for scanning said scan test word into said portion of the integrated circuit;

output means connected to said portion of the integrated circuit for receiving a test response to said scan test word therefrom; and

output register means connected to said output means for storing said test response and transmitting aid test response via said parallel bus.

8. The test circuit set forth in claim 7, wherein said output means is connected to said output register means by a multi-conductor bus which connects a plurality of monitor bits within said test response to a plurality of storage locations within said output register means for storing said test response therein in a parallel data transfer.

9. The test circuit set forth in claim 7, wherein said output means is connected to said output register means by a single-conductor bus which serially transfers said test response to a plurality of storage locations within said output register means for storing said test response therein.

10. For use in a digital integrated circuit having an address decoder and a data bus a test circuit comprising:

a control register having a plurality of parallel inputs, each connected to a respective control storage location, and each control storage location connected to a respective output, for receiving a control bit into at least one of said locations;

scan clock means connected to the address decoder for generating a scan clock output in response to a write instruction to a preselected address;

scan data input register means, having a plurality of data storage locations, connected to the data bus for receiving a scan data word therefrom;

said scan data input register having a shifted serial output controlled by said scan clock means for outputting said scan data word as a sequence of serial bits;

scan path connection means responsive to at least one of said control bits connected to said scan data register means for receiving and outputting said sequence of serial bits to a logically connected scan path;

means for assembling said sequence of serial bits into a scan data word for testing a digital logic element of said integrated circuit;

scan path means connected to said assembling means for scanning said scan data word as a multi-bit input into said digital logic element of the integrated circuit;

means connected to the integrated circuit for receiving an output of said digital logic element responsive to said multi-bit input; and

output register means connected to said digital logic element to receive said output therefrom for storing said output and transmitting said output to the data bus.

11. The test circuit set forth in claim 10, wherein said output means is connected to said output register means by a multi-conductor bus which connects a plurality of monitor bits within said test response to a plurality of storage locations within said output register means for storing said test response therein in a parallel data word transfer.

12. The test circuit set forth in claim 10, wherein said output means is connected to said output register means by a single-conductor bus which serially transfers said test response to a plurality of storage locations within said output register means for storing said test response therein.

13. A method for testing a portion of an integrated circuit having an address decoder and a data bus, comprising the steps of:

a. storing a scan path control word in a control register connected to the data bus;

b. generating a scan clock signal in response to a plurality of write instructions to a preselected address;

c. receiving a scan data word from the data bus and storing said scan data word in a scan data register;

d. shifting said scan data word out of said scan data register as a sequence of serial data bits in response to said scan clock signal;

e. logically connecting a scan path according to said scan path control word and communicating said sequence of serial data bits over said scan path;

f. assembling said sequence of serial data bits into a scan test word;

g. scanning said scan test word into said portion of the integrated circuit;

h. receiving a test response to said scan test word from said portion of the integrated circuit; and

i. transmitting said test response to the data bus.

14. The method set forth in claim 13, after step h, further comprising the steps of:

receiving a second scan data word from the data bus and storing said second scan data word in said scan data register;

shifting said second scan data word out of said scan data register as a second sequence of serial data bits in response to said scan clock signal;

assembling said second sequence of serial data bits into a second scan test word;

scanning said second scan test word into said portion of the integrated circuit;

receiving a second test response to said second scan test word from said portion of the integrated circuit; and

logically combining said second test response with said first test response into a test response.