Method for fabricating semiconductor devices by use of an N.sup.+ buried layer for complete isolation

• US 5,116,777 A
• Filed: 04/30/1990
• Issued: 05/26/1992
• Est. Priority Date: 04/30/1990
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Original Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Inventors: Zamanian, Mehdi, Chan, Tsiu C.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US07/516,287
• Time in Patent Office: 757 Days
• Field of Search: 437/26, 437/56, 437/57, 437/31, 437/34, 437/33, 437/63, 437/27, 437/54, 437/59, 437/74-77, 357/44, 357/43, 357/36, 148/DIG. 9, 148/DIG. 85, 148/DIG. 87
• US Class Current: 438/234
• CPC Class Codes: H01L 21/74 Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components

Abstract

An N⁺ buried layer is formed under all the N-channel devices in the memory array of an integrated circuit device. The N⁺ buried layer can also be formed under N-channel input/output devices. The N⁺ buried layers include contacts to the power supply. Such a device layout provides for complete isolation of the memory array from the remainder of the circuitry. The isolation of the N-channel input/output devices also provides for enhanced immunity to input/output noise.

Claims

1. A method for fabricating a semiconductor memory device, comprising the steps of:

forming an N-type buried layer in a substrate;

forming an epitaxial silicon layer above said buried layer;

forming a plurality of P-type regions in said epitaxial layer;

forming a plurality of contacts to said N-type buried layer through said epitaxial layer wherein the plurality of contacts are spaced at regular intervals throughout the memory array; and

forming an array of N-channel field effect devices in said P-type regions.

2. The method of claim 1, wherein the contacts comprise N-type diffusions through the epitaxial layer.

3. The method of claim 1, wherein at least one additional contact to the N-type buried layer forms a continuous structure around a memory array.

4. The method of claim 1, further comprising the steps of:

forming N-type buried layers in locations wherein input/output N-channel devices are to be formed;

forming input/output P-type regions over such N-type buried layers;

forming contacts to the input/output buried layers through the input/output P-type regions; and

forming N-channel input/output devices in the input/output P-type regions.

5. A method for fabricating semiconductor integrated devices, comprising the steps of:

forming an N-type buried layer and a P-type buried layer in a substrate;

forming an epitaxial silicon layer above said buried layers;

forming a plurality of P-type regions in said epitaxial layer at least one over said N-type buried layer;

forming at least one contact to said N-type buried layer through said epitaxial layer; and

forming at least one N-channel field effect device in said at least one P-type region over said N-type buried layer.

6. The method of claim 5, wherein the at least one contact comprises N-type diffusions through the epitaxial layer.

7. The method of claim 5, further comprising the step of:

forming N-type buried collector layers under the epitaxial layer in which NPN transistors are to be formed.

8. The method of claim 7, further comprising the step of:

when the at least one contact is formed to the N-type buried layer, also forming N-type diffusions to contact the buried collector layers.

9. The method of claim 5, wherein the at least one contact to the N-type buried layer forms a continuous structure around a memory array.

10. The method of claim 5, further comprising the steps of:

forming N-type buried layers in locations wherein input/output N-channel devices are to be formed;

forming input/output P-type regions over such N-type buried layers;

forming contacts to the input/output buried layers through the input/output P-type regions; and

forming N-channel input/output devices in the input/output P-type regions.

11. A method for fabricating semiconductor integrated devices, comprising the steps of:

forming an N-type buried layer in a substrate;

forming an epitaxial silicon layer above said buried layer;

forming a plurality of P-type regions in said epitaxial layer;

forming a contact to said buried layer through said epitaxial layer, said contact forming a continuous structure around a memory array, and

forming a plurality of N-channel field effect devices in said P-type regions.

12. The method of claim 11, further comprising the steps of:

forming N-type buried layers in locations wherein input/output N-channel devices are to be formed;

forming input/output P-type regions over said N-type buried layers;

forming contacts to the input/output buried layers through the input/output P-type regions; and

forming N-channel input/output devices in the input/output P-type regions.

13. The method of claim 11 wherein the contacts comprise N-type diffusions through said epitaxial layer.

14. The method of claim 11, further comprising the step of:

forming N-type buried collector layers under the epitaxial layer in which NPN transistors are to be formed.

15. The method of claim 14, further comprising the step of:

when the plurality of contacts are formed to said buried collector layers, also forming N-type diffusions to contact the buried collector layers.