Video signal and output device for freeze-frame video telephone

• US 5,117,286 A
• Filed: 09/07/1990
• Issued: 05/26/1992
• Est. Priority Date: 09/09/1989
• Status: Expired due to Fees

• Current Assignee: Electronics and Telecommunications Research Institute, Korea Telecommunication Authority
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Jeong, Ju H.
• Primary Examiner(s): Kostak, Victor R.
• Application Number:
  US07/578,879
• Time in Patent Office: 627 Days
• Field of Search: 358/85, 358/105, 358/181, 358/134, 358/153, 379/53, 379/54
• US Class Current: 348/14.12
• CPC Class Codes: H04N 5/907 using static stores, e.g. storage tubes or semiconductor memories H04N5/91 takes precedence
• CPC Class Codes: H04N 7/24 Systems for the transmission of television signals using pulse code modulation H04N21/00 takes precedence

Abstract

A video input and output device which generates sampling frequency synchronized to the video signal, and stores video image of 256 grey levels, 8 bits wide, per pixel in memory after realtime sampling and quanitization following the selection of the necessary part of the input video signal. The invention also adopts a two-dimensional addressing technique for the simplification of the hardware structure, and can easily redefine the size of the video image for following future trends.

Claims

1. A video input and output device for a freeze-frame video phone, which inputs video data for transmission from a camera and outputs video data to a monitor, comprising;

a bus;

a host connection means connected to the bus so as to allow checking of control and operation status of the equipment by a CPU,

a mode control signal generation means connected to the host connection means, which receives control signal from the host connection means and generates a bypass mode signal, a display mode signal, an acquisition mode signal, and a video image size signal for controlling each operation;

a synchronization signal separation circuit which separates an input composite video signal into a vertical synchronization signal, a horizontal synchronization signal, a composite synchronization signal, an odd/even field signal, and a burst signal;

a PLL (Phase-Locked Loop) circuit which generates a signal with frequency of 384 times the horizontal synchronization signal from the synchronization signal separation circuit;

a window signal generation means connected to the PLL circuit, which selects a part of video image size out of an input video signal;

address buffer means connected to the bus, the window signal generation means, and the mode control signal generation means, which generates address for access of a video image data storage memory;

a first analog interface means for reception of the input video signal;

an A/D (Analog to Digital) converter connected to the first analog interface means;

a data buffer means connected to the bus and the A/D converter and the mode control signal generator, which transmits and receives data to and from the video image data storage memory;

a multiplexer connected to the data buffer means, the A/D converter, and the mode control signal generator;

a D/A converter which converts a digital signal from the multiplexer into an analog signal; and

a second analog interface means connected to the D/A converter.

2. A video input and output device according claim 1, wherein the window signal generation means comprises a vertical window generator and a horizontal window generator, each of which generators respectively comprises a counter, a programmable array logic circuit connected to the counter, and a flip-flop circuit connected to the programmable array logic circuit.

3. A video input and output device according to claim 1, wherein the address buffer means includes an address generator which comprises a line address generator and a pixel address generator.