Memory address mechanism in a distributed memory architecture

• US 5,117,350 A
• Filed: 12/15/1988
• Issued: 05/26/1992
• Est. Priority Date: 12/15/1988
• Status: Expired due to Fees

• Current Assignee: Flashpoint Computer Corporation
• Original Assignee: Flashpoint Computer Corporation
• Inventors: Thomas, James H., Hilpert, Edwin J. Jr., Peiffer, Robert E. Jr., Parrish, Osey C.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Loomis, John C.
• Application Number:
  US07/284,529
• Time in Patent Office: 1,258 Days
• Field of Search: 364/200, 364/900
• US Class Current: 711/1
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163

Abstract

A computer system having plural nodes interconnected by a common broadcast bus. Each node has memory and at least one node has a processor. The system has a dynamically configurable memory which may be located within the system address space of a distributed system architecture including memory within each node having a processor and the memory resident within other nodes. The memory in the system address space is addressable by system physical addresses which are isolated from the physical addresses for memory in each node. The node physical addresses are translatable to and from the system physical addresses by partition maps located in partition tables at each node. Memory located anywhere in the distributed system architecture may be partitioned dynamically and accessed on a local basis by programming the partition tables, stored in partitioning RAMs. The use of the partitioning process permits data to be duplicated throughout a distributed system architecture and permits read cycles for shared data to execute at local bus speeds.

Claims

1. In a distributed processing system comprising read/write path means for carrying memory address and data information and connecting a plurality of nodes, each node comprising at least computer means and local memory connected by a local bus and means for partitioning said memory into one or more partitions, the method of a first node writing in a broadcast mode to one or more other nodes comprising:

at said first node;

addressing a local memory partition with a local physical address;

converting said partition location physical address to a system physical address;

writing to said system physical address on said read/write path; and

at said others of said plurality of nodes;

detecting said system physical address from said read/write path,

converting said system physical address to a local memory partition address, and

writing to the local memory partition at each said other nodes.

2. In a distributed processor system having a plurality of nodes, at least two of said nodes having a computer connected by a primary bus to a local memory comprising a local addressable space having physical addresses, said nodes being connected by an interface to a secondary bus for carrying value and message transactions, said nodes further including an address translator and together defining a system physical address space;

the method of establishing distributed common memory comprising;

at a first node;

establishing in its local physical memory a local memory partition having local memory addresses;

identifying a system address space partition, corresponding to said local memory address partition;

loading its address translator with said local physical and system physical memory addresses; and

informing other nodes to establish similar partitions by message transaction broadcast on said secondary bus; and

at each other of said plurality of nodes;

responding to said first node information concerning the establishment of a local memory partition by establishing in its local memory a local memory partition;

identifying the system physical address space corresponding to said local physical memory address partition; and

loading its address translator with said local physical and system physical memory addresses.

3. In a distributed processor system having a plurality of nodes, at least two of said nodes having a computer connected by a primary bus to a local memory comprising a local addressable space, said nodes being connected by an interface to a secondary bus operative to carry value and message transactions,

the method of establishing shared global memory comprising:

at a first node at which a distributed common memory is physically resident;

establishing in its local memory a local physical memory partition having a local memory address;

establishing a system physical address space partition, corresponding to said local memory address partition;

informing other nodes that said partition has been established by message transactions broadcast on said secondary bus; and

loading an address translator with said local physical and system physical addresses; and

at each other of said plurality of nodes at which said distributed common memory is not physically resident,

responding to said first node message information by establishing a non-present memory a local memory partition having a local physical memory address;

identifying said system address space with said local physical memory address; and

loading said address translator with said local physical and system physical memory addresses.

4. The system of claim 3 wherein said shared global and remote global memory is accessed through communications path writes and reads.

5. In a distributed processing system having an interconnect bus for carrying value and message transfers among a plurality of nodes in a broadcast mode, each of which comprises a computer means and an address conversion means and at least one of which comprises memory, a method for the computer means at a first node to address the memory in at least one of a plurality of second nodes comprising:

generating at said first node a first node logical address;

converting said first node logical address to a first node physical address;

converting said first node physical address to a system physical address;

transmitting said system physical address to said plurality of nodes via said interconnect bus;

receiving said system physical address at said plurality of second nodes, including said at least one node having memory;

converting said system physical address to a second node physical address; and

using said second node physical address to address said second node memory.

6. The method of claim 5 wherein said first node physical address comprises a first and second address portion and said method further comprises:

providing said first portion to said first interface means;

said converting step comprises providing said second portion to said address conversion means, said address conversion means comprising a programmable store having third address portions;

outputting a third address portion to said interface in response to said second address portion; and

combining said first and third address portions into a system physical address.

7. The method of claim 5 wherein said first node physical address to system physical address conversion step comprises reading out a stored system physical address in response to an input first node physical address.

8. The method of claim 5 wherein said system physical address to node physical address conversion step comprises reading out a stored second node physical address in response to an input system physical address.

9. The method of claim 5 further comprising creating partitions in said memory in at least one node,said partitions having local physical addresses and being identifiable by system physical addresses.

10. The method of claim 9 further comprising allocating various ones of said partitions to selected memory (tasks) as required and deallocating those allocated partitions that are not required.

11. The method of claim 9 further comprising the steps of:

creating a system partition and creating a local partition prior to creating said system partition.

12. A data communications system, having a system address space, comprising:

a common communications path for carrying information as message and value transactions;

a plurality of communication nodes connected by said path, each of said nodes comprising computing means, memory comprising a local address space identified by local physical addresses, interface means connecting said computing means and memory to said common path, each of said nodes being operative via said interface means to broadcast data and system address information to a plurality of said nodes via said common path and to detect data and system physical address information present on said path, and address translation means operative to convert local memory physical addresses into system physical addresses and to convert system physical addresses to local memory physical addresses, whereby the computing means of a first node can write into memory of a second node as a local first node write operation.

13. The data communication system of claim 12 further comprising:

remote global memory means having addressable memory forming a part of said system address space.

14. The data communication system of claim 12 wherein said local memory at each node is divisible under control of said computing means into distributed common memory and shared global memory.

15. The data communication system of claim 12 wherein said address translation means performs local to system address conversions on the basis of blocks of memory addresses.

16. A distributed processing system comprising:

read/write path means for carrying information as message and value transactions,

a plurality of nodes operative to read from or write to said path means, said plurality of nodes comprising;

at least a first node comprising first computing means, first memory means comprising a first local address space identified by first local physical addresses, first local bus means, said first local bus means providing a communications path for said first computing means and first memory means within said node, and first interface means for interfacing said first node to said read/write path means,

at least a second node comprising second memory means comprising a second local address space identified by second local physical addresses and second interface means for interfacing said second node to said read/write path means, and

means for dynamically partitioning said first memory means and allocating selected ones of the first memory partitions and said second memory means into a system address space identified by system physical addresses, said first computing means being operative to perform read/write operations in said system address space using a local physical address of said node;

wherein each of said first nodes comprises address translation means responsive to at least certain of said physical addresses in said first local address space for translating a local physical address into a system physical address in said system address space and address translation means responsive to at least certain of said system physical addresses for translating said system physical addresses to respective local physical addresses.

17. The system of claim 16 wherein said second node comprises address translation means responsive to addresses in said system address space for translating a system physical address into a physical address in said second local address space.

18. The system of claim 16, or claim 17 wherein said address translation means comprises at least one partition RAM for identifying said first memory partitions.

19. The system of claim 16 or claim 17 wherein said address translation means is modifiable by selectively loading said means with local physical address and system physical address information.

20. The system of claim 16 wherein said second node further comprises at least a second computing means, second local bus means providing a communications path for said second computing means and said second memory means within said node and second interface means for interfacing said second node to said read/write path means.

21. The system of claim 16 further comprising a plurality of said first nodes, each said first node having a partitioning means and the first memory means in each said first node being dynamically partitionable by said partitioning means in response to message information from computing means at any first node whereby the system memory capacity, as defined by said system address space, may be allocated to individual first nodes.

22. The system of claim 16 wherein said address translation means comprises a system resource manager and a partition RAM operatively connected to said system resource manager, said manager comprising a processor for programming address translation information into said partition RAM.

23. The system of claim 22 wherein said system resource manager at each said first node maintains a record of the allocation of memory in said first memory means at said first node.

24. The system of claim 22 wherein each said system resource manager comprises means for creating a partition in said local memory, means for attaching said memory partition in said local memory, means for detaching an attached memory partition and means for deleting a partition in said local memory.

25. The system of claim 16 comprising a plurality of first nodes wherein said system address space comprises any one or more of remote global memory distributed common memory and shared global memory.

26. The system of claim 16 comprising a plurality of first nodes wherein the computing means at any first node can command the partitioning of memory at any other first node by message transactions on said read/write path and can perform read/write operations to partitioned memory at any other first node by value transactions.

27. The system of claim 16 further comprising cache memory at a node, said memory being operative to cache data in said system address space, regardless of the particular node at which said cache memory is physically located.

28. The system of claim 27 wherein at least one of said nodes further comprises cache memory said cache being operative to cache both local memory writes and remote memory writes.

29. The system of claim 16 wherein said second node comprises a global memory resource occupying at least a part of said system address space, said global memory resource being accessible by any processor in any of said first nodes via a physical system address.

30. The system of claim 16 wherein said first computing means comprises a digital computer.

31. The system of claim 16 wherein said first memory means on any first node having a first local address may be addressed by said computing means in any other first node as a local read/write operation to a local address which need not be said first local address.

32. The system of claim 16 wherein at least one of said first computers is allocated at least a defined portion of said system address space and can cache any area of said defined address space.

35. The system of claims 16 or 33, wherein said local memory for said respective first nodes may be of dissimilar sizes.

33. A distributed processing system comprising:

(i) read/write path means for broadcasting memory address and data information,

(ii) a plurality of first nodes operative to read from and write to said path means, each first node comprising computing means, local memory and local bus means connecting said computing means, and said local memory and

(iii) system memory means, said system memory means being resident on at least one second nodes and comprising at least one of;

remote global memory, said memory being resident on said at least one second node and being operatively connected to said communications path and being accessible as system physical address space via said path by the computer means in said first nodes,

shared global memory, said memory being resident on one of said first nodes and being accessible as system physical address space by the computer means in any other of said first nodes, and

distributed common memory, said memory being resident on one or more selected said first nodes and being accessible as system physical address space having the same physical address for all of selected first nodes.

34. The system of claim 33 wherein said distributed common memory is written into via said communications path write transfers and is read through local read cycles.