Buffer for packetizing block of data with different sizes and rates received from first processor before transferring to second processor

• US 5,117,486 A
• Filed: 04/21/1989
• Issued: 05/26/1992
• Est. Priority Date: 04/21/1989
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hughes, James E., Clark, Alan R., Valashinas, James W., Higham, Joseph P.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Lim, Krisna
• Application Number:
  US07/341,503
• Time in Patent Office: 1,131 Days
• Field of Search: 364/200, 364/900, 395/250, 395/275
• US Class Current: 710/307
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

A bus-to-bus adapter is provided for coupling the input/output bus of a first data processor to the input/output bus of a second and different type of data processor. The adapter enables the transfer of data and messages from the first processor to the second processor and vice versa. The adapter includes a buffer storage unit and control logic for enabling multiple data buffers to be provided for enabling multiple independent data transfer operations to be performed in a concurrent manner. The control logic also includes a mechanism for allowing the reading out of data from a data buffer to begin before such data buffer has received all of its incoming data. The adapter further includes a programmable service time allocation mechanism for limiting message service time relative to data transfer service time and for providing different amounts of data transfer service time for different ones of the multiple data buffers.

Claims

1. A communications adapter for coupling a first data processor to a second data processor, said communications adapter comprising:

buffer storage means for receiving and storing data supplied by said first data processor at a time, rate and location controlled by said first data processor, which data is en route to said second data processor;

transfer control means, coupled to said buffer storage means, for tracking the amount and location of said data received from said first data processor and stored in said buffer storage means, dynamically packetizing said data, and transferring a resultant packet of said data from said buffer storage means to said second data processor when said buffer storage means contains enough of said data to form said resultant packet, said transfer control means transferring said data from said first data processor to said buffer storage means in units or blocks of different size than said resultant packet, said transfer control means continuing the transfer of additional data from said first data processor to said buffer storage means while packetizing said data into said resultant packet and transferring said resultant packet of data from said buffer storage means to said second data processor; and

wherein a capacity of said buffer storage means for said data received from said first data processor is many times greater than a size of one of said packets; and

said first data processor has a different architecture than said second data processor, the architecture of said second data processor usually requiring receipt of data in said resultant packets whereas the architecture of said first data processor not requiring transmission of data in said resultant packets.

2. A communications adapter as set forth in claim 1 wherein said transfer control means transfers additional packets of said data from said buffer storage means to said second data processor when said buffer storage means contains enough of said data to form said additional packets.

3. An adapter as set forth in claim 2

wherein said transfer control means includes means for establishing a first data buffer area in said buffer storage means for transfer of one type of data from said first data processor to said second data processor, and a second data buffer area in said buffer storage means for transfer of another type of data from said first data processor to said second data processor;

and

further comprising means for selecting a first number of packets of data to be transferred from said first data buffer area to said second data processor, and selecting a second number of packets of data to be transferred from said second data buffer area to said second data processor; and

wherein said transfer control means is coupled to receive the selections of said first number and said second number, transfers said first number of packets of data from said first data buffer area to said second processor, then halts transfer of packets from said first data area to said second data processor even if there is sufficient data in said first data buffer area to form an additional packet, and then transfers said second number of packets of data from said second data buffer area to said second processor.

4. An adapter as set forth in claim 2 further comprising means for disabling said transfer control means from transferring said packets of data to said second data processor such that data received by said buffer storage means from said first data processor accumulates in said buffer storage means, and receiving an enable for said transfer control means to enable said transfer control means to transfer to said second data processor in packets said data accumulated within said buffer storage means.

5. An adapter as set forth in claim 1 wherein said transfer control means interleaves the transfer of said packet of data from said buffer storage means to said second data processor with the transfer of said additional data from said first data processor to said buffer storage means.