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Memory addressing system using first and second address signals and modifying second address responsive predetermined values of first address signal

  • US 5,117,492 A
  • Filed: 10/12/1989
  • Issued: 05/26/1992
  • Est. Priority Date: 11/03/1988
  • Status: Expired due to Fees
First Claim
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1. A computer memory addressing system, said addressing system comprising:

  • an external memory including a plurality of memory units, each of said memory unit containing a plurality of blocks of memory locations;

    means for supplying first address signals indicative of sets of said blocks of memory locations which reside in one or more of said plurality of memory units;

    means for supplying second address signals;

    a first logic circuit means, responsive to said first address signals and said second address signals, for generating enabling signals for respective ones of said memory units;

    a second logic circuit means, responsive to predetermined values of said first address signal, for modifying one bit of at least one of said second address signals;

    a second logic circuit means including means, responsive to a first address signals and either said second address signals, or said second address signal modified in response to predetermined vales of said first address signal, for generating access signals for respective ones of said blocks of memory locations in an enabled one of said memory units; and

    one block of memory locations in one of said memory units, including means for permitting access by an unmodified one of said second address signals only.

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