Memory addressing system using first and second address signals and modifying second address responsive predetermined values of first address signal

• US 5,117,492 A
• Filed: 10/12/1989
• Issued: 05/26/1992
• Est. Priority Date: 11/03/1988
• Status: Expired due to Fees

• Current Assignee: Lucas Industries Public Limited Company Well Street Birmingham B19 2XF England
• Original Assignee: Lucas Industries Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Inventors: Nash, Alan J.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): DONAGHUE, LARRY D
• Application Number:
  US07/420,321
• Time in Patent Office: 957 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70

Abstract

A computer has a pageable memory which comprises a plurality of memory units each made up of a plurality of blocks of addressable memory locations. A designated one of the blocks is required to be accessed in combination with the remainder of the blocks. Logic circuits are responsive to first and second groups of address bits to generate signals which enable a selected one of the memory units and access a selected one of the blocks on the selected unit. The designated block is accessed directly by one of the aforesaid groups of address bits.

Claims

1. A computer memory addressing system, said addressing system comprising:

an external memory including a plurality of memory units, each of said memory unit containing a plurality of blocks of memory locations;

means for supplying first address signals indicative of sets of said blocks of memory locations which reside in one or more of said plurality of memory units;

means for supplying second address signals;

a first logic circuit means, responsive to said first address signals and said second address signals, for generating enabling signals for respective ones of said memory units;

a second logic circuit means, responsive to predetermined values of said first address signal, for modifying one bit of at least one of said second address signals;

a second logic circuit means including means, responsive to a first address signals and either said second address signals, or said second address signal modified in response to predetermined vales of said first address signal, for generating access signals for respective ones of said blocks of memory locations in an enabled one of said memory units; and

one block of memory locations in one of said memory units, including means for permitting access by an unmodified one of said second address signals only.

2. A system as claimed in claim 1 wherein at least one memory unit includes means for permitting access by predetermined values of said second address signals only.

3. A method of addressing a computer memory, said memory comprises a plurality of memory units, each of said memory units includes a plurality of blocks of memory location, said method comprising:

supplying first address signals indicative of sets of said blocks of memory locations which reside in one or more of said plurality of memory units;

supplying second address signals;

generating enabling signals for respective ones of said memory units in response to said first and second address signals;

modifying said second address signals in response to predetermined values of said first address signal to provide signals for accessing respective ones of said blocks of memory location in an enabled one of said memory units, in response to said first and either second address signals or said modified second address signals, and

accessing one block in one of said memory units by an unmodified one of said second address signals only.

4. A computer memory addressing system, said addressing system comprising:

a central processor;

an external memory including a plurality of memory units, each memory unit containing blocks of memory locations;

means for supplying a first address signal indicative of sets of said blocks of memory locations which reside in one or more of said plurality of memory units;

means for supplying at least one second address signal, said at least one second address signal comprises two bits;

first and second logic circuits responsive to said first address signal and said at least one second address signal;

said first logic circuit means for generating enabling signals for respective ones of said plurality of memory units;

said second logic circuit including means for modifying one bit of said at least one second address signal in response to predetermined values of said first address signal;

said modified at least one second address signal comprising means for providing access signals for respective ones of said blocks in an enabled one of said plurality of memory units;

at least one of said memory units and one of said blocks being accessible by two respective unmodified values of said two bits of said at least one second address signal only.