CMOS current mirror with offset adaptation

• US 5,119,038 A
• Filed: 02/04/1991
• Issued: 06/02/1992
• Est. Priority Date: 12/09/1988
• Status: Expired due to Term

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Allen, Timothy P., Mead, Carver A., Anderson, Janeen D. W., Wall, Michael F.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/650,577
• Time in Patent Office: 484 Days
• Field of Search: 330/2, 330/288, 323/315, 323/316
• US Class Current: 330/2
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/303 using a switching device H03F1/305, H03F3/005, H03F3/38 take precedence
• CPC Class Codes: H03F 3/45479 characterised by the way of common mode signal rejection
• CPC Class Codes: H03F 3/45753 using switching means, e.g. sample and hold
• CPC Class Codes: H03F 3/45977 using switching means, e.g. sample and hold

Abstract

An MOS current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures in order to adapt the current mirror to supply a desired output current when a particular input calibration current is present.

Claims

1. An adaptable MOS current mirror integrated on a semiconductor substrate, including:

an input node,

an output node,

first and second MOS transistors, each having a source, a gate, and a drain,

a first MOS capacitor having first and second electrodes,

the source of said first MOS transistor being connected to a source of fixed voltage, the gate and drain of said first MOS transistor being connected to said input node and to said first electrode of said first MOS capacitor, the source of said second MOS transistor being connected to a source of fixed voltage, the gate of said second MOS transistor comprising a floating node connected to said second electrode of said first capacitor, the drain of said second MOS transistor forming said output node,

means for generating a first electrical control signal,

electron removal means coupled to said floating node and responsive to said first electrical control signal for removing electrons from said floating node, said electron removal means operating to vary the rate of removal of electrons from said floating gate in response to the magnitude of said first electrical control signal,

means for selectively supplying a calibration current to said input node during adaptation,

means for selectively supplying a desired output current to said output node during adaptation,

means for generating a second electrical control signal during adaptation,

electron injecting means coupled to said floating node and responsive to said second electrical control signal for injecting electrons on to said floating node, said electron injection means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said second electrical control signal,

whereby the output current of said current mirror is adapted to be equal to said desired output current when its input current is equal to said calibration current.

2. The adaptable MOS current mirror of claim 1 wherein said electron injecting means is a non-avalanche hot electron injection device including:

a p-type region in said semiconductor substrate,

an n-type region disposed in said p-type region,

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region,

means for applying a negative potential to said p-region, said negative potential having a magnitude of greater than about 3.2 volts relative to said floating gate,

means for applying a positive potential to said n-type region with resect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region,

means for injecting electrons into said p-type region,

whereby said first and second positive potentials act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.

3. The adaptable MOS current mirror of claim 1 wherein said second control signal is a monotonic function of the difference between the actual output current of said current mirror and said desired output current, whereby said adaptable current mirror operates to made said actual output current equal to said desired output current.

4. The adaptable mos current mirror of claim 1 wherein said second electrical control signal is a monotonic function of the voltage on said floating node.

5. The adaptable MOS current mirror of claim 1 wherein said electron injecting means is a semiconductor structure for performing hot electron injection.

6. The adaptable MOS current mirror of claim 5 wherein said electron injection means is a non-avalanche hot electron injection device including:

a p-type region in said semiconductor substrate,

a n-type region disposed in said p-type region,

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region,

means for applying a first positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region,

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region,

mean for injecting electrons into said p-type region,

whereby said first and second positive potentials act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.