Comprehensive logic circuit layout system

• US 5,119,313 A
• Filed: 06/29/1990
• Issued: 06/02/1992
• Est. Priority Date: 08/04/1987
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Houston, Theodore W., Kalyan, Vibhu, Bosshart, Patrick, Shaw, Ching-Hao, Matzke, Douglas
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Cosimano, Edward R.
• Application Number:
  US07/546,612
• Time in Patent Office: 704 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 326/38
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

Random logic circuitry (210) is laid out in a logic array (212) that has a plurality of row and column locations. The logic circuitry (210) implements a plurality of dynamic logic circuits, each logic circuit having a plurality of logic gate field effect transistors (224) each formed at a selected intersection of one of the row locations and a predetermined plurality of the column locations. Elongate gate conductors (584-602) are formed at selected row locations in the logic array (212), each gate conductor provided as a gate for one or more of the logic gate transistors (224). Selected ones (e.g. 514, 544) of the transistors are merged in a row direction if the logic does not require them to be isolated from one another. A plurality of elongate second conductors (222) interconnect to selected ones of the sources or drains of the transistors (224). Non-Boolean portions of the logic circuitry are formed in an adjacent tile section (214) in the semiconductor layer separate from the logic array (212). A plurality of river-routed conductors (e.g. AL, F, LL) each connect together a respective array terminal (710, 712), and a terminal of a respective non-Boolean tile.

Claims

1. A random logic array including static gates and dynamic gates, formed at a face of a semiconductor layer for implementing a plurality of logic equations comprising:

a plurality of row location and column locations;

each logic equation having a plurality of logic gate transistors each formed at a selected intersection of one of said row location with a fixed plurality of adjacent column locations, each trasistor having a current path including first and second source/drain areas;

at least one logic equation sharing common logic terms with another logic equation, said shared common logic terms being a portion of the logic expressed by said at least one logic equation and said another logic equation; and

a plurality of elongate current path conductors each formed at a selected column location for coupling together current paths of selected ones of said transistors, each said current path conductor connected to at least one of said first and second source/drain areas at a single column location thereof.

2. The logic array of claim 1, wherein said current path conductors are less than one-half the width of said logic gate transistors, said first and second source/drain areas of each transistor occupying at least two column locations;

and

said first and second source/drain areas of each said transistor having space for the connection of at least two of said current path conductors to the corners thereof.

3. The logic array of claim 1, wherein selected ones of said transistors are fused in a row direction, the first source/drain area of a first of said fused transistors continuous with the first source/drain area of a second of said fused transistors, the second source/drain area of said first transistor continuous with the second source/drain area of said second transistor;

and

at least one of said continuous first and second source/drain areas having a plurality of said current path conductors connected thereto.

4. The logic array of claim 1, wherein each current path conductor has parallel elongate columnar boundaries, each transistor having parallel columnar boundaries, at least one columnar boundary of each current path conductor being colinear with a columnar boudary of a transistor connected by the last said current path conductor.

5. The random logic array of claim 1, wherein said logic equations each comprise at least one logic term generally disposed in a columnar direction in said logic array;

each logic term comprising at least one transistor group, each transistor group comprising transistors sharing the same adjacent column locations and disposed in adjaccent row locations.

6. The logic array of claim 1, and further comprising:

a plurality of elongate gate conductors each disposed at a gate conductor row location, each gate conductor insulatively disposed over at least one transistor between first and second source/drain areas thereof;

a plurality of contacts each made a corner of a selected source/drain area for connection of a current path conductor to said selected source/drain area, the row location of each of said contacts disposed between the row locations of next adjacent gate conductors.

7. The logic array of claim 6, wherein the row location of each of said contacts is disposed approximately one-half of the columnar distance from a first adjacent gate conductor row location to a second adjacent conductor row location.

8. A random logic circuit comprising:

a logic array including static gates and dynamic gates, said logic array processing Boolean operations and including more than two levels of logic;

A tile section including a plurality of tiles, said tile section processing non-Boolean operations, and including routing connections for transfer of signals within and without said tile section, and

a plurality of river-routed conductors interspersed throughout said logic array, each conductor coupled to at least one gate transistor in said logic array and to a tile, said river-routed conductors comprising first level conductors insulatively disposed on said face, and second level conductors insulatively disposed over said first level conductors.

9. The logic circuit of claim 8, wherein said tile section is formed near a first side of said logic array, a second tile section formed at a second side of said array, first- and second-level river-routed conductors formed for connecting said second tile section to said logic array.

10. The logic circuit of claim 8, wherein said first level conductors are formed of polycrystalline silicon, said second level conductors formed in a first metallization step.

11. The logic circuit of claim 8, and further comprising:

a plurality of first terminals disposed within said logic array;

a corresponding plurality of second terminals disposed at an edge of said tile section, each first terminal and a respective second terminal forming a terminal pair;

said terminal pairs divided into first level pairs and second level pairs, first level conductors predominately used to connect together said first level pairs, second level conductors used to connect second level pairs.

12. A random logic circuit as recited in claim 8 which further comprises:

a first circuit block formed at said face and having a plurality of first terminals, each first terminal having an x-coordinate and a y-coordinate;

a second circuit block formed at said face opposite a side of said first circuit block and having a plurality of second terminals, each second terminal having an x-coordinate and a y-coordinate, the x-coordinate of each second terminal being different from the x-coordinate of the remaining second terminals, the x-coordinate of each first terminal being different from the x-coordinate of the remaining first terminals;

each first terminal and a respective second terminal forming a terminal pair, a river-routed conductor connecting the terminals of each terminal pair;

said terminal pairs comprising first level pairs and second level pairs, each first level pair predominately routed in a first level of conductors insulatively disposed over said face, each second level pair routed in a second level of conductors insulatively disposed over said first level.

13. The circuit of claim 8, wherein said river-routed conductors connect first terminals disposed at predetermined coordinates inside said logic array and respective second terminals disposed in said tile section;

said gate transistors each formed around predetermined x- and y-coordinates in said logic array, the y-coordinates of said second terminals greater than the y-coordinates of said gate transistors, selected ones of said first terminals having y- coordinates less than at least one of said gate transistors.

14. The logic circuit of claim 13, wherein said first terminals each have an x-coordinate different from the remaining first terminals, said second terminals each having an x-coordinate different from the remaining second terminals.

15. The logic circuit of claim 11, wherein at least one conductive lead connecting a first level pair is comprised of a second level conductor segment and a first-level conductor segment, a contact made between said first level conductor segment and said second level conductor segment.

16. The logic circuit of claim 15, wherein said conductive lead is routed from said first terminal at a first conductor level until an obstacle at said first level is encountered, said conductor lead then connectively switched to a second conductor level to avoid said obstacle, said conductive lead connectively switched back to said first level once said second level conductor reaches a selected location where no first level obstacles are present.

17. The logic circuit of claim 15, wherein a first level conductor segment and a second level conductor segment are used as portions of a conductive lead to connect a first level terminal pair, said second level segment routed from a first terminal of the last said terminal pair to an interlevel contact, said contact made from an end of said second level conductor segment to an end of a first level conductor segment, said first level segment routed to said second terminal, said contact located above any array obstacle immediately disposed to a selected side direction from said contact.