Semiconductor integrated circuit device

• US 5,119,314 A
• Filed: 11/28/1989
• Issued: 06/02/1992
• Est. Priority Date: 02/17/1986
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Hotta, Takashi, Iwamura, Masahiro
• Primary Examiner(s): Lall, Pharshotam S.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US07/442,301
• Time in Patent Office: 917 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 307/443, 307/446, 307/451, 307/454, 307/570, 357/34, 357/42, 357/43
• US Class Current: 716/104
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/11896 using combined field effect/bipolar technology
• CPC Class Codes: Y10S 257/923 with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio

Abstract

A semiconductor integrated circuit device which can operate at high speed and involves a low power consumption and a high integration density, wherein a Bi-CMOS basic cell and a Bi-CMOS macro cell are employed to define a critical path and a CMOS basic cell and a CMOS macro cell are employed for a portion of the device other than the critical path.

Claims

1. A method of manufacturing a standard cell semiconductor integrated circuit device incorporating a first macro cell including CMOS gates without bipolar gates and a second macro cell including bipolar and CMOS gates comprising:

a function design step;

a logic design step where a desired logic according to said function design step is assembled using logical macro cells included in a prepared logical cell library;

evaluating a plurality of paths for said semiconductor integrated circuit device, and determining at least a first path which has a delay time greater than a predetermined delay time specification;

allotting physical cells to the logical macro cells with reference to a physical cell library where a set of a plurality of physical cells having the same logic function including the first macro cell and the second macro cell are prepared, wherein the first macro cell is allotted in areas of said integrated circuit other than said first path and wherein the second macro cell is allotted in a portion of the integrated circuit which defines said first path to reduce delay time along said first path; and

returning to said logic design step when the predetermined delay time specification is not satisfied even by the allotment of the second macro cell in said first path.

2. A method of manufacturing according to claim 1, wherein the first path has the largest delay time of the plurality of evaluated paths.

3. A method of manufacturing a standard cell semiconductor integrated circuit device incorporating a first polycell including CMOS gates without bipolar gates and a second polycell including bipolar and CMOS gates comprising:

a function design step;

a logic design step where a desired logic according to said function design step is assembled using logical polycells included in a prepared logical cell library;

evaluating a plurality of paths for said semiconductor integrated circuit device, and determining at least a first path which has a delay time greater than a predetermined delay time specification;

allotting physical cells to the logical polycells with reference to a physical cell library where a set of a plurality of physical cells having the same logic function including the first polycell and the second polycell are prepared, wherein the first polycell is allotted in areas of said integrated circuit other than said first path and the second polycell is allotted in a portion of the integrated circuit which defines said first path to reduce delay time along said first path; and

returning to said logic design step when the predetermined delay time specification is not satisfied even by the allotment of the second polycell in said first path.

4. A method of manufacturing according to claim 3, wherein the first path has the largest delay time of the plurality of evaluated paths.

5. A method of manufacturing a standard cell semiconductor integrated circuit device incorporating a first macro cell including CMOS gates without bipolar gates, a second macro cell including bipolar and CMOS gates, a first polycell including CMOS gates without bipolar gates and a second polycell including bipolar and CMOS gates comprising:

a function design step;

a logic design step where a desired logic according to said function design step is assembled using logical macro cells and logical polycells including in a prepared logic cell library;

evaluating a plurality of paths for said semiconductor integrated circuit device, and determining at least a first path which has a delay time greater than a predetermined delay time specification;

allotting physical cells to the logical macro cells with reference to a physical cell library where a set of a plurality of physical cells having the same logic function including the first macro cell and the second macro cell are prepared, wherein the first macro cell is allotted in areas of said integrated circuit other than said first path and the second macro cell is allotted in a portion of the integrated circuit which defines said first path to reduce delay time along said first path;

allotting physical cells to the logical polycells with reference to a physical cell library where a set of a plurality of physical cells having the same logic function including the first polycell and the second polycell are prepared, wherein the first polycell is allotted in areas of said integrated circuit other than said first path and said second polycell is allotted in a portion of the integrated circuit which defines said first path to reduce delay time along said first path; and

returning to said logic design step when the predetermined delay time specification is not satisfied even by the allotment with the second macro cell and the second polycell in said first path.

6. A method of manufacturing according to claim 5, wherein the first path has the largest delay time of the plurality of evaluated paths.