Register bus multiprocessor system with shift
First Claim
1. A digital data processing apparatus comprisingA. bus means for transferring packets of information-representative digital signals, said bus means including shift register means comprising a plurality of digital storage and transfer stages connected in series in a ring configuration for sequentially storing and transferring said information-representative digital signals, wherein each said stage within said shift register means includes means for storing an information-representative signal of (M) bits, where (M) is greater than one,B. a plurality of processing cells, connected in a ring configuration through said bus means, each processing cell being in communication with an associated subset of (N) said stages, where (N) is greater than one, at least one of said cells having associated memory means coupled thereto for storing a plurality of information-representative digital signals.C. said at least one said processing cell further including cell interconnect means, connected to said associated subset of stages and said associated memory means, for selectively transferring information-representative signals between said associated subset of stages and said associated memory means,D. said cell interconnect means including means for performing at least one of modifying, extracting, replicating and transferring a packet of digital information-representative signals, wherein at least a portion of said packet is stored within said associated subset of stages, based on an association, if any, between an information-representative signal identified in that packet and one or more information-representative signals of said plurality of information-representative signals stored in said associated memory means, andE. said cell interconnect means including means responsive to applied digital clock cycle signals for simultaneously transferring at least a selected digital signal packet through successive stages of said associated subset o stages, at a rate responsive to said digital clock cycle rate, while performing said at least one modifying, extracting, replicating and transferring operation on that same digital signal packet.
1 Assignment
0 Petitions
Accused Products
Abstract
A digital data processing apparatus includes a shift-register bus that transfers packets of digital information. The bus has a plurality of digital storage and transfer stages connected in series in a ring configuration. A plurality of processing cells, each including at least a memory element, are connected in a ring configuration through the bus, with each cell being in communication with an associated subset of stages of the bus. At least one processing cell includes a cell interconnect that performs at least one of modifying, extracting, replicating and transferring a packet based on an association, if any, between a datum identified in that packet and one or more data stored in said associated memory element. The cell interconnect responds to applied digital clock cycle signals for simultaneously transferring at least a selected packet through successive stages of the bus at a rate responsive to the digital clock cycle rate, while performing the modifying, extracting, replicating and transferring operation.
72 Citations
17 Claims
-
1. A digital data processing apparatus comprising
A. bus means for transferring packets of information-representative digital signals, said bus means including shift register means comprising a plurality of digital storage and transfer stages connected in series in a ring configuration for sequentially storing and transferring said information-representative digital signals, wherein each said stage within said shift register means includes means for storing an information-representative signal of (M) bits, where (M) is greater than one, B. a plurality of processing cells, connected in a ring configuration through said bus means, each processing cell being in communication with an associated subset of (N) said stages, where (N) is greater than one, at least one of said cells having associated memory means coupled thereto for storing a plurality of information-representative digital signals. C. said at least one said processing cell further including cell interconnect means, connected to said associated subset of stages and said associated memory means, for selectively transferring information-representative signals between said associated subset of stages and said associated memory means, D. said cell interconnect means including means for performing at least one of modifying, extracting, replicating and transferring a packet of digital information-representative signals, wherein at least a portion of said packet is stored within said associated subset of stages, based on an association, if any, between an information-representative signal identified in that packet and one or more information-representative signals of said plurality of information-representative signals stored in said associated memory means, and E. said cell interconnect means including means responsive to applied digital clock cycle signals for simultaneously transferring at least a selected digital signal packet through successive stages of said associated subset o stages, at a rate responsive to said digital clock cycle rate, while performing said at least one modifying, extracting, replicating and transferring operation on that same digital signal packet. - View Dependent Claims (2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
-
15. A digital data processing apparatus according to claim 13, wherein as the number of stages of said shift register means increases, the flux of said digital words through said stages of said shift register means remains constant.
-
16. A digital data processing apparatus according to claim 13, wherein clock cycle skew associated with said at least one set of digital clock cycles remains substantially constant with reference to each of said (N) stages of said shift register means as the number (N) increases.
-
17. A digital data processing apparatus according to any of claims 1 - 3, wherein said cell interconnect means includes at least one of
A. insert buffer means for storing at least a selected digital signal packet for transfer to at least one stage of said associated subset of stages for insertion into said shift register means, and B. second buffer means for storing at least a selected digital signal packet extracted from said associated subset of stages.
-
3. A digital data processing apparatus comprising
A. bus means for transferring packets of information-representative digital signals, said bus means including shift register means comprising a plurality of digital storage and transfer stages connected in series in a ring configuration for sequentially storing and transferring said information-representative digital signals, wherein each said stage within said shift register means includes means for storing an information-representative signal of (M) bits, where (M) is greater than one, B. a plurality of processing cells, connected in a ring configuration through said bus means, each processing cell being in communication with an associated subset of (N) said stages, where (N) is greater than one, at least one of said cells having associated memory means coupled thereto for storing information-representative digital signals, C. said at least one said processing cell further including cell interconnect means, connected to said associated subset of stages and said associated memory means, for selectively transferring information-representative signals between said associated subset of stages and said associated memory means, and D. said cell interconnect means including means responsive to applied digital clock cycle signals for simultaneously transferring at least a selected digital signal packet through successive stages of said associated subset of stages, at a rate responsive to said digital clock cycle rate, while performing at least one modifying, extracting, replicating and transferring operation on that same digital signal packet.
Specification