Flight system for converting 12 volts 32-bit INS data into 5 volts 8-bit data pattern in real time

• US 5,119,482 A
• Filed: 12/18/1989
• Issued: 06/02/1992
• Est. Priority Date: 12/18/1989
• Status: Expired due to Fees

• Current Assignee: United States Of America As Represented By The Secretary Of The Air Force
• Original Assignee: United States Of America As Represented By The Secretary Of The Air Force
• Inventors: Lloyd, John W. F.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): PAN, DANIEL H
• Application Number:
  US07/452,662
• Time in Patent Office: 897 Days
• Field of Search: 364/200, 364/900, 364/449, 364/452, 364/460, 370/112, 382/41
• US Class Current: 710/307
• CPC Class Codes: G06F 13/4018 with data-width conversion
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002

Abstract

An inertial Navigation System (INS) data interface box allows the transfer of INS data to standard commercial computer (i.e. Personal Computer or PCs) for flexible in-flight use of data received from the INS. The data box includes a means connected to the data bus for changing the INS output from 12 to 5 volts. The data of interest is then applied to a Label/Decode circuit which in turn directs the data to a Write Address Generator circuit which then applies the data to a Page One Memory Buffer circuit. After the data is filed in the Page One Memory Buffer, the Write Address Generator directs a Page Control circuit to turn to a Page Two Memory Buffer to accept the next cycle of data. During the interim data can be read out of the Page One buffer and converted to 8 bit words for applications to the PC. Should the 8 Bits Converter be processing data, "page flips" is inhibited to prevent readout from the Page Two Buffer from mutilating Page One Buffer data as it is being read out. The PC requests a cycle of data by sending a "P" to Bit Converter circuit causing the Read Address Generator to read a cycle of data out of the Page Memory Buffer which is not accepting input data.

Claims

1. A flight data transfer system for use in combination with an inertial navigation system which produces output signals composed of 32 bit words which include:

latitude, longitude, true heading and ground speed, said flight data transfer system making the output signals of said inertial navigation system accessible to a personal computer in real time, wherein said inertial navigation system produces its output signals on an INS bus at a 12 volt level, and wherein said flight data transfer system comprises;

a buffer which is electrically connected with said INS bus to receive the output signals of the inertial navigation system therefrom, said buffer reducing the inertial navigation system signals to a 5 volt level and producing output signals composed of serial 32 bit words;

a label decode circuit which is electrically connected to said buffer and which receives said serial 32 bit words therefrom, said label decode circuit breaking up each of said serial 32 bit words into first, second, third and fourth 8 bit words and sending said first 8 bit word to said identifying means since the first 8 bit word always identifies the contents of the 32 bit words;

a series to parallel circuit which is electrically connected with said label decode circuit, and which outputs said second, third and fourth 8 bit words from said label decode circuit;

a memory which receives, stores and outputs said 8 bit output signals produced by said series to parallel circuit to produce output signals thereby;

a means for identifying the 8 bit output signals of said memory by their contents, said identifying means identifying the contents of the 8 bit output signals that contain latitude, longitude, true heading and ground speed; and

an interface which electrically connects said memory to said personal computer to provide the output signals of said memory to said personal computer.

2. A flight data transfer system, as defined in claim 1, wherein said identifying means comprises:

a write address generator which receives and forwards said first 8 bit word from said label decode circuit to said memory; and

a read address generator which receives and forwards said first 8 bit word from said write address generator to said universal asynchronous received and transmit chip.