Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation

• US 5,119,485 A
• Filed: 05/15/1989
• Issued: 06/02/1992
• Est. Priority Date: 05/15/1989
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Reininger, Russell A., Ledbetter, William B. Jr.
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Elmore, Reba I.
• Application Number:
  US07/351,898
• Time in Patent Office: 1,114 Days
• Field of Search: 364/200, 364/900, 395/400, 395/425
• US Class Current: 711/146
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)

Abstract

A bus snoop control method for maintaining coherency between a write-back cache and main memory during memory accesses by an alternate bus master. The method and apparatus incorporates an option to source `dirty` or altered data from the write-back cache to the alternate bus master during a memory read operation, and simultaneously invalidate `dirty` or altered data from the write-back cache. The method minimizes the number of cache accesses required to maintain coherency between the cache and main memory during page-out/page-in sequences initiated by the alternate bus master, thereby improving system performance.

Claims

1. A method for implementing a data bus snoop controller in a data processing system having a processor coupled to a data bus by a bus interface control circuit, the system being utilized by at least one alternate data bus master coupled to the data bus to maintain coherency between a write-back cache memory in the processor and a system memory during a data transfer wherein data is transferred between one of the write-back cache memory or the system memory and the alternate bus master via the data bus, said method comprising the step of:

coupling an encoded control signal from the at least one alternate data bus master to the bus interface control circuit via the data bus to selectively enable data bus snooping in the system wherein said data bus is snooped or monitored during said data transfer in response to a request by the alternate bus master for data stored in a predetermined cache entry in said write-back cache memory, said method further comprising the steps of;

in response to the bus interface control circuit detecting a first value of the control signal;

(1) supplying data from said predetermined cache entry if said bus snooping detects a read operation initiated by said alternate data bus master; and

(2) simultaneously marking said predetermined cache entry as invalid of empty;

or

in response to the bus interface control circuit detecting a second value of the control signal;

(1) determining if the predetermined cache entry has been previously modified and thereby placed in a dirty state, and one of;

(2) if the predetermined cache entry is in the dirty state, supplying said data from said predetermined cache entry if said bus snooping detects a read operation initiated by said alternate data bus master and not invalidating said predetermined cache entry;

or

(3) if the predetermined cache entry is not in the dirty state, not supplying said data from said predetermined cache entry.

2. The method of claim 1 wherein a processor write of new data to the system memory that results in a cache hit is handled by writing said new data only to said write-back cache.

3. The method of claim 1 wherein a processor write of new data to the system memory that results in a cache hit is handled by writing said new data to both said write-back cache and to the system memory.

4. The method of claim 1 wherein said method for maintaining coherency between said cache memory and said system memory is utilized in a uniprocessor computing system with a single cache. PG,28

5. The method of claim 1 wherein said alternate bus master comprises a Direct Memory Access unit coupled to a permanent data storage means.

6. A method for implementing a data bus snoop controller utilized by an alternate data bus master coupled to a data bus, the bus snoop controller functioning to maintain coherency between a write-back cache memory of a data processor coupled to the data bus via a bus interface control circuit and a system memory also coupled to the data bus, the data bus snoop controller operating during a data bus transfer wherein data is transferred via the data bus, said method comprising:

coupling an encoded control signal from the alternate data bus master to the bus interface control circuit via the data bus to selectively inhibit snooping or monitoring of said data bus during said data bus transfer in response to the bus interface control circuit detecting a first encoded value of the encoded control signal;

detecting a second encoded value of the encoded control signal with the bus interface control circuit wherein said data bus is snooped or monitored during said data bus transfer, said method when the second encoded valve is detected further comprising the steps of;

said alternate bus master selectively requesting a write operation of data to a first predetermined address;

verifying and indicating that the first predetermined address is a first predetermined cache entry within the write-back cache;

marking said first predetermined cache entry as invalid or empty in response to writing data to the write-back cache memory; and

supplying data from said first predetermined cache entry in response to said alternate bus master selectively requesting a read operation of data and in response to verifying and indicating that the requested data is at the first predetermined cache entry, the data having an identifier indicating that the data has been altered by earlier processor activity and said identifier not being modified;

detecting a third encoded value of the control signal with the bus interface control circuit wherein said data bus is snooped or monitoring during said data bus transfer, said method when the third encoded value is detected further comprising the steps of;

said alternate bus master selectively requesting a write operation of data to a second predetermined address;

verifying and indicating that the second predetermined address is a second predetermined cache entry within the write-back cache;

marking said second predetermined cache entry as invalid or empty, and supplying data to said second predetermined cache entry in response to said alternate bus master requesting the write operation; and

marking said second predetermined cache entry as clean or valid simultaneously with the supplying of data in response to said alternate bus master selectively requesting a read operation of data and in responsea to verifying and indicating that the requested data is at the second predetermined cache entry; and

detecting a fourth encoded value of the control signal with the bus interface control circuit wherein said data bus is snooped or monitored during said bus transfer, said method when the fourth encoded value is detected further comprising the steps of;

said alternate bus master selectively requesting a write operation of data to a third predetermined address;

verifying and indicating that the third predetermined address is a third predetermined cache entry within the write-back cache;

making said third predetermined cache entry as invalid or empty and supplying data to said third predetermined cache entry in response to said alternate bus master requesting to write operation; and

marking said third predetermined cache entry as invalid or empty and supplying data from said third predetermined cache entry in response to said alternate bus master selectively requesting a read operation of data and in response to verifying and indicating that the data to be read is in the write-back cache memory.

7. The method of claim 6 wherein a processor write of new data to the system memory that results in a cache hit is handled by writing said new data only to said write-back cache.

8. The method of claim 6 wherein said method for maintaining coherency between said cache memory and said system memory is utilized in a uniprocessor computing system with a single cache.

9. The method of claim 7 wherein said alternate bus master further comprises a Direct Memory Access unit coupled to a permanent data storage means.

10. The method of claim 6 wherein said bus snoop controller is further controlled by a second control signal provided by the bus interface control circuit and which indicates whether said bus transfer is a write or read request.

11. A method for maintaining coherency between a cache memory and a main memory coupled via a data bus in a virtual memory system during a page-out/page-in sequence performed by an alternate data bus master coupled to the data bus and to a permanent data storage means, said method comprising the steps of;

performing a page-out transfer operation wherein a first page of data is transferred from said main memory and written to said permanent data storage means, said pageout transfer operation further comprising the steps of;

coupling a bus interface control circuit to the cache memory and to the data bus;

coupling an encoded control signal from the alternate bus master to the bus interface control circuit and using the bus interface control circuit to detect one of at least two values of the control signal;

snooping or monitoring the data bus during the pageout transfer operation and in response to a read request from the alternate bus master for data which is stored in a predetermined cache entry in said cache memory, and one of;

(1) marking said predetermined cache entry as invalid or empty and simultaneously supplying the data from said predetermined cache entry to the permanent data storage means in response to a first value of the control signal;

or

(2) in response to a second value of the control signal, only supplying the data from said predetermined cache entry to the permanent data storage means if the predetermined cache entry has been previously modified, the predetermined cache entry not being marked as invalid; and

performing a page-in transfer operation wherein a second page of data is transferred from said permanent data storage means and written to said main memory, said page-in transfer operation further comprising the step of;

inhibiting said data bus snooping of said data bus with a third value of the control signal during said page-in transfer operation.

12. The method of claim 11 wherein said cache memory is a write-back cache wherein a processor write of new data to main memory that results in a cache hit is handled by writing said new data only to said write-back cache.

13. The method of claim 11 wherein said cache memory is a write-through cache wherein a processor write of new data to main memory that results in a cache hit is handled by writing said new data to both said write-through cache and to main memory.

14. The method of claim 11 wherein said method for maintaining coherency between said cache memory and said main memory during said page-out/page-in sequence is utilized in a single processor computing system with a single cache memory.