Process for self aligning a source region with a field oxide region and a polysilicon gate

• US 5,120,671 A
• Filed: 11/29/1990
• Issued: 06/09/1992
• Est. Priority Date: 11/29/1990
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lu, Wen-Juei, Tang, Daniel N.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US07/621,284
• Time in Patent Office: 558 Days
• Field of Search: 357/23.5, 437/41, 437/43, 437/63, 437/69, 437/70, 437/915, 437/984, 148/DIG. 70
• US Class Current: 438/257
• CPC Class Codes: H01L 21/76202 using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO H01L21/76235 takes precedence; together with vertical isolation, e.g. LOCOS in a SOI substrate, H01L21/76264
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device. This method and apparatus allows reduced memory cell size and improved device density by substantially eliminating the bird'"'"'s beak encroachment and corner rounding effects usually found between neighboring cells due to inadequacies in the prior art photolithography process. This method and apparatus is particularly appropriate for use with EPROM, Flash EPROM, EEPROM, or other types of memory cells and in periphery devices.

Claims

1. In a semiconductor device having a silicon substrate, a method of forming source regions in said silicon substrate said source regions self-aligned with polysilicon regions and field oxide regions, said method comprising:

a) forming continuous substantially parallel field oxide regions on said silicon substrate;

b) forming continuous substantially parallel gate oxide regions on said silicon substrate between said field oxide regions;

c) forming continuous substantially parallel polysilicon regions on said continuous substantially parallel field oxide regions and on said continuous substantially parallel gate oxide regions, said continuous substantially parallel polysilicon regions being substantially perpendicular to said continuous substantially parallel field oxide regions and to said continuous substantially parallel gate oxide regions;

d) etching said continuous substantially parallel field oxide regions and said continuous substantially parallel gate oxide regions exposed between said continuous substantially parallel polysilicon regions using a high selectivity oxide etch;

e) forming said self-aligned source regions in select portions of said silicon substrate exposed between said continuous substantially parallel polysilicon regions and said etched field oxide regions.

2. The method of claim 1 wherein in step (a) said field oxide regions are thermally grown.

3. The method of claim 2 wherein in step (b) said gate oxide regions are thermally grown.

4. The method of claim 3 wherein in step (c) said continuous substantially parallel polysilicon regions are formed by chemically depositing polysilicon and etching select portions of said polysilicon.

5. The method of claim 4 wherein in step (f) said source regions are formed using ion implantation.

6. The method of claim 5 wherein in step (f) said select portions of said silicon substrate exposed between said continuous substantially parallel polysilicon regions and said etched field oxide regions are selected by forming a mask over non-select portions of said silicon substrate exposed between said continuous substantially parallel polysilicon regions and said etched field oxide regions.

7. The method of claim 6 wherein said etching process in step (e) is achieved with a plasma etch process using a radio frequency (RF) power of 1200 watts.

8. The method of claim 7 wherein said etching process in step (e) is achieved with a plasma etch process having an atmospheric pressure of 50 mTorr.

9. The method of claim 8 wherein said etching process in step (e) is achieved with a plasma etch process having a gas mixture and flow rate of 75 standard cubic centimeters per minute (SCCM) of CHF3 to 5 SCCMs of O2.

10. The method of claim 9 wherein said self-aligned source regions are source regions of an EPROM device.

11. The method of claim 10 wherein said EPROM device is a Flash EPROM device.

12. The method of claim 1 wherein said etching process in step (e) is achieved with a plasma etch process using a radio frequency (RF) power of 1200 watts.

13. The method of claim 12 wherein said etching process in step (e) is achieved with a plasma etch process having an atmospheric pressure of 50 mTorr.

14. The method of claim 13 wherein said etching process in step (e) is achieved with a plasma etch process having a gas mixture and flow rate of 75 standard cubic centimeters per minute (SCCM) of CHF3 to 5 SCCMs of O2.

15. The method of claim 14 wherein said self-aligned source regions are source regions of an EPROM device.

16. The method of claim 14 wherein said self-aligned source regions are source regions of a Flash EPROM device.