Driver circuit for converting a CMOS level signal to a high-voltage level

• US 5,120,991 A
• Filed: 01/12/1990
• Issued: 06/09/1992
• Est. Priority Date: 05/16/1988
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takahashi, Nobuyuki
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): OUELLETTE, SCOTT
• Application Number:
  US07/457,771
• Time in Patent Office: 879 Days
• Field of Search: 307/370, 307/242, 307/570, 307/296.1, 340/718, 340/789, 340/803, 340/811
• US Class Current: 327/108
• CPC Class Codes: H03K 17/0406 in composite switches
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/567 Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT

Abstract

There is disclosed a driver circuit for driving a flat panel display. In this invention, a gate bias for a MOS transistor for charging an output terminal to high level is generated by a constant voltage element. The value of a current supplied to the constant voltage element is controlled by a current control circuit. In order to turn off the charging MOS transistor, a MOS transistor for discharging the node of the gate of the charging MOS transistor is set in an ON state. In order to switch an output, two drive signals are output from a drive signal generator to turn off both the charging MOS transistor for charging the output terminal to high level and the discharging MOS transistor for discharging the output terminal to low level.

Claims

1. A driver circuit comprising:

a first MOS transistor having a source, a gate, and a drain, one of the source and drain being connected to a first power source voltage;

a diode connected between the other of said source and drain of said first MOS transistor and an output terminal;

a second MOS transistor having a source, a gate, and a drain, the drain and the source being respectively connected to said output terminal and a ground voltage, and the gate receiving a first drive signal;

a constant voltage element inserted between the gate of said first MOS transistor and the other of said source and drain of said first MOS transistor;

a third MOS transistor having a source, a gate, and a drain, the drain and the source being respectively connected to said gate of said first MOS transistor and the ground voltage, and the gate receiving a second drive signal;

a bipolar transistor having an emitter, a collector, and a base, wherein the emitter is connected to the first power source voltage and the collector is connected to said gate of said first MOS transistor;

current control means, for controlling a value of current supplied to the base of said bipolar transistor in accordance with a plurality of third drive signals; and

drive signal generating means, for generating the first drive signal, the second drive signal, and the plurality of third drive signals on the basis of an input signal and a control signal.

2. A driver circuit according to claim 1, wherein said first, second, and third MOS transistors are double diffusion n-channel MOS transistors.

3. A driver circuit according to claim 1, wherein said constant voltage element is a Zener diode, an anode of which is connected to the other of said source and drain of said first MOS transistor and a cathode of which is connected to said gate of said first MOS transistor.

4. A driver circuit according to claim 1, wherein said current control means comprises:

a fourth MOS transistor having a source, a gate, and a drain, wherein one of the source and drain is connected to said base of said bipolar transistor, and the gate receives a second power source voltage;

a plurality of first resistors, each having a first terminal connected to the other of said source and drain of said fourth MOS transistor, said plurality of first resistors each having different resistances; and

a plurality of fifth MOS transistors, each having a source, a gate, and a drain, wherein one of said source and drain is connected to a second terminal of a corresponding one of said plurality of first resistors, the other of said source and drain of said plurality of fifth MOS transistors is connected to the ground voltage, and wherein each gate of said plurality of fifth MOS transistors receives one of said plurality of third drive signals.

5. A driver circuit according to claim 4, wherein said current control means includes two of said plurality of first resistors to supply different three-value currents, including a current value of zero to said base circuit of said bipolar transistor.

6. A driver circuit according to claim 4, wherein said fourth MOS transistor is a double diffusion n-channel MOS transistor, and said plurality of fifth MOS transistors are enhancement n-channel MOS transistors.

7. A driver circuit according to claim 1, wherein said drive signal generating means generates the second drive signal to turn ON said third MOS transistor in synchronism with a timing at which said second MOS transistor is maintained in an OFF state in response to the first drive signal.

8. A driver circuit according to claim 7, wherein said drive signal generating means generates the first and second drive signals to turn ON said third MOS transistor a predetermined period of time before turn-on of said second MOS transistor, and generates the first and second drive signals to turn OFF said third MOS transistor a predetermined period of time after turn-off of said second MOS transistor.

9. A driver circuit according to claim 4, wherein said bipolar transistor is a pnp multicollector transistor having first and second collectors, said pnp multicollector transistor having an emitter which is connected to the first power source voltage, and a base which is connected to said first collector and one of said source and drain of said fourth MOS transistor, said second collector being connected to said gate of said first MOS transistor, a second resistor being connected between said base of said multicollector transistor and the first power source voltage.

10. A driver circuit according to claim 4, wherein said bipolar transistor is a pnp transistor having a single collector, said pnp transistor having an emitter which is connected to the first power source voltage and a base which is connected to one of said source and drain of said fourth MOS transistor, said single collector being connected to said gate of said first MOS transistor, a second resistor being connected to said base of said pnp transistor and the first power source voltage.