Synaptic element and array

• US 5,120,996 A
• Filed: 06/06/1990
• Issued: 06/09/1992
• Est. Priority Date: 03/10/1989
• Status: Expired due to Term

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Anderson, Janeen D. W., Allen, Timothy P., Faggin, Federico, Mead, Carver A.
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US07/535,283
• Time in Patent Office: 734 Days
• Field of Search: 307/201, 307/353, 307/264, 307/493, 340/825.79, 340/825.83, 340/825.85, 340/825.86, 340/825.87, 340/825.88, 340/825.89, 340/825.9
• US Class Current: 327/94
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence

Abstract

An electronic circuit is disclosed having a sample/hold amplifier connected to an adaptive amplifier. A plurality of such electronic cicuits may be configured in an array of rows and columns. An input voltage vector may be compared with an analog voltage vector stored in a row or column of the array and the stored vector closest to the applied input vector may be identified and further processed.

Claims

1. An electronic circuit fabricated as a part of an integrated circuit, said integrated circuit having a portion containing active circuits, including in combination:

an adaptive amplifier having a gain of magnitude much larger than 1, said amplifier including;

an output node,

an inverting input node, said input node being a floating node forming the gate of at least one MOS transistor,

a first capacitor for coupling an input to said circuit to said floating node, said first capacitor having a first electrode connected to said input to said circuit and a second electrode connected to said floating node,

a second capacitor connected from said output node to said floating node, said second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node,

an opaque layer covering at least said portion of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor,

a sample/hold circuit having an input, a select input, and an output, said output connected to said first electrode of said first capacitor.

2. The electronic circuit of claim 1 wherein the sample/hold circuit is a five-transistor transconductance amplifier having a capacitor connected between said output and a source of fixed voltage.

3. The electronic circuit of claim 1 wherein said sample/hold circuit comprises a pass-transistor having a gate, a source and a drain, and a capacitor, said source of said pass-transistor being said input of said sample/hold circuit, said drain of said pass-transistor being said output of said sample/hold circuit, said capacitor connected between said output and a source of fixed voltage, and said gate of said pass-transistor being the select input of said sample/hold circuit.

4. An electronic circuit fabricated as a part of an integrated circuit, said integrated circuit having a portion containing active circuits, including in combination:

an adaptive amplifier having a gain of magnitude much larger than 1, and including;

an output node,

an inverting input node, said input node being a floating node forming the gate of at least one MOS transistor,

a first capacitor for coupling an input to said circuit to said floating node, said first capacitor having a first electrode connected to said input to said circuit and a second electrode connected to said floating node,

a second capacitor connected from said output node to said floating node, said second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node,

an opaque layer covering at least said portion of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor,

sample/hold circuit means, connected to said first electrode of said first capacitor, for selectively storing an analog voltage at the input node of said adaptive amplifier.

5. An electronic circuit fabricated as a part of an integrated circuit, said integrated circuit having a portion containing active circuits, including in combination:

an adaptive amplifier having a gain of magnitude much larger than 1, and including;

a non-inverting input node,

an inverting input node,

an output node;

a floating node,

a first MOS input transistor, having its gate connected to said non-inverting input node,

a second MOS input transistor, having its gate connected to said floating node, and its source connected to the source of said first MOS input transistor,

current source means for supplying a bias current to the source of said first and second MOS input transistor,

current mirror means, connected to the drains of said first and second MOS input transistors, for developing an output voltage proportionate to the difference between currents flowing in the drains of said first and second MOS input transistors,

a first capacitor having a first electrode connected to said inverting input node and a second electrode connected to said floating node,

a second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node,

an opaque layer covering said portion of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor,

a sample/hold circuit having an input, a select input, and an output, said output connected to said inverting input node of said adaptive amplifier.

6. The circuit of claim 5, further including means for selectively connecting together said inverting input node and said non-inverting input node.

7. The electronic circuit of claim 5 wherein said sample/hold circuit comprises a pass-transistor having a gate, a source and a drain, and a capacitor, said source of said pass-transistor being the input of said sample/hold circuit, said capacitor connected between said output and a source of fixed voltage, said drain of said pass-transistor being the output of said sample/hold circuit, and said gate of said pass-transistor being the select input of said sample/hold circuit.

8. The circuit of claim 5 wherein said sample/hold circuit is a five-transistor transconductance amplifier having a capacitor connected between said output and a source of fixed voltage.

9. An electronic circuit fabricated as a part of an integrated circuit, said integrated circuit having a portion containing active circuits, including in combination:

an adaptive amplifier having a gain of magnitude much larger than 1, and including;

an input node,

an output node,

an MOS N-channel transistor and an MOS P-channel transistor, said MOS N-channel transistor having a source connected to a source of negative voltage, and its drain connected to the drain of said MOS P-channel transistor and to said output node, the source of said MOS P-channel transistor connected to a source of positive voltage,

a floating gate common to said MOS N-channel transistor connected to a source of positive voltage,

a first MOS capacitor having a first electrode connected to said input node and a second electrode comprising a portion of said floating gate,

a second MOS capacitor having a first electrode connected to said output node and a second electrode comprising a portion of said floating gate,

an opaque layer covering said portion of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor,

a sample/hold circuit having an input, a select input, and an output, said output connected to said input node of said adaptive amplifier.

10. The electronic circuit of claim 9 wherein said sample/hold circuit comprises a pass-transistor having a gate, a source and a drain, and a capacitor, said source of said pass-transistor being the input of said sample/hold circuit, said capacitor connected between said output and a source of fixed voltage, said drain of said pass-transistor being the output of said sample/hold circuit, and said gate of said pass-transistor being the select input of said sample/hold circuit.

11. The circuit of claim 9 wherein said sample/hold circuit is a five-transistor transconductance amplifier having a capacitor connected between said output and a source of fixed voltage.

12. An array of electronic circuits arranged in rows and columns, each of said electronic circuits including an adaptive amplifier having an input node and an output node and means for generating an error current, and a sample/hold circuit having an input, an output, and a select input, the output of said sample/hold circuit connected to the input node of said adaptive amplifier, the select inputs of all sample/hold circuits associated with the electronic circuits in a given column of said array connected in common to one of a plurality of write lines, and the error current generated from each adaptive amplifier in a column connected in common to one of a plurality of output sense lines, and the inputs of all the sample/hold circuits in a row of said array connected in common to one of a plurality of input voltage lines.

13. The array of claim 12 wherein said means for generating an error current generates an error current decreasing monotonically with error and further including:

write decoder means connected to said plurality of write lines for selectively activating one of said write lines at a time,

a plurality of sense amplifiers, one of said sense amplifiers having its input connected to each of said sense lines, and

means connected to the outputs of said sense amplifiers for indicating which one of said plurality of output sense lines is drawing more current than the other ones of said plurality of output sense lines.

14. The array of claim 12 wherein said means for generating an error current generates an error current increasing monotonically with error and further including:

write decoder means connected to said plurality of write lines for selectively activating one of said write lines at a time,

a plurality of sense amplifiers, one of said sense amplifiers having its input connected to each of said sense lines, and

means connected to the outputs of said sense amplifiers for sensing which one of said plurality of output sense lines is drawing less current than the other ones of said plurality of output sense lines.