Ferroelectric capacitor memory circuit MOS setting and transmission transistor

• US 5,121,353 A
• Filed: 07/06/1990
• Issued: 06/09/1992
• Est. Priority Date: 07/06/1989
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Natori, Kenji
• Primary Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/548,823
• Time in Patent Office: 704 Days
• Field of Search: 365/117, 365/145, 365/149, 365/189.01, 357/23.6
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A memory circuit including a plurality of ferroelectric capacitors arranged in a matrix, setting MOS field effect transistors for setting both electrodes of each of the ferroelectric capacitor at the same electric potential, and transmission MOS field effect transistors for transmitting information to the ferroelectric capacitors, and having a construction in which two word lines are provided corresponding to each line of the ferroelectric capacitors, one bit line is provided corresponding to each row of the ferroelectric capacitors, each of the transmission MOS field effect transistors is connected to one of the word lines and the bit line, and each of the setting MOS field effect transistors is connected to the other word line. Also disclosed is a memory circuit including memory cells each composed of ferroelectric capacitors arranged in a matrix and transmission MOS field effect transistors provided corresponding to the ferroelectric capacitors for transmitting information to the ferroelectric capacitors, line address decoders each provided corresponding to each group of the memory cells in each line for controlling the input and output of information to the ferroelectric capacitors, word lines provided corresponding to each group of memory cells in each the line for selecting line, and drive lines for commonly controlling the ferroelectric capacitors in the group of memory cells, and having a construction in which the word lines and the drive lines are connected to the line address decoders, and bit lines are provided corresponding to each row of the memory cells.

Claims

1. A memory circuit, having ferroelectric capacitors, comprising:

a plurality of storage means, arranged in a matrix, each storage means of said plurality of storage means comprising a ferroelectric capacitor, having two electrodes, for storing data as a polarization state of said ferroelectric capacitor;

transmission means, provided in said each storage means, for transmitting said data to and for reading said data into said each storage means; and

setting means, provided in said each storage means, for keeping said two electrodes of said ferroelectric capacitor at the same electrical potential when said each storage means is not accessed;

said transmission means being connected to said setting means and to one electrode of said each storage means; and

said setting means being connected to both of said two electrodes of said ferroelectric capacitor in said each storage means.

2. A memory circuit according to claim 1, further including:

a first word line and a second word line provided for each row of said plurality of storage means; and

a bit line provided for each column of said plurality of storage means;

each said transmission means being connected to said first word line and to said bit line; and

each said setting means being connected to said second word line.

3. A memory circuit according to claim 1, wherein said setting means and said transmission means comprise MOS field effect transistors.

4. A memory circuit according to claim 1, wherein each said ferroelectric capacitor of said storage means comprises lead zircon-titanate.