Integrated data link controller with synchronous link interface and asynchronous host processor interface
First Claim
1. A data link control device, for connection between a data communication network and a parallel information transfer bus, said network having multiple data communication channels for concurrent communication of data signals relative to terminals remote from said device, said device having multiple internal channels, associatable with said network channels, for processing data signals in transit between respective said network channels and said parallel bus, said bus connectable to an external data processing system and to an external memory associated with said system, said device thereby interfacing between said network and both said external system and external memory, via said bus, said device comprising:
- logic circuits partitioned into synchronous and asynchronous circuit sections;
circuits in said synchronous section operating in time division multiplex, in cyclically recurrent time slots assignable to said internal channels of said device, for transferring data signals between said network channels and said internal device channels;
said asynchronous section operating to transfer data signals between internal device channels and said external memory in asynchronous relation to occurrences of time slots assigned to respective internal channels in the synchronous section;
internal memory means connected to both said synchronous and asynchronous circuit sections for storing communication data signals in transit between said synchronous and asynchronous sections relative to said internal channels;
said synchronous section processing data signals in said internal channels in transit between respective said network channels and said internal memory means, and conducting said processing in synchronous relation to times of occurrence of respective said time division time slots assigned to respective internal channels in said synchronous section;
said asynchronous section directing transfers of said data signals between said internal memory means and said external memory, via said bus, said data signals being transferred relative to respective said internal channels but in asynchronous time relation to times of recurrence of time slots assigned in said synchronous section to respective internal channels; and
coordinating means interfacing between said synchronous and asynchronous sections, for instigating transfers of data signals relative to said internal channels by said asynchronous section, between said internal memory means and external memory, in response to request signals from said synchronous section, said coordinating means thereby instigating asynchronous transfers of data signals relative to said internal channels, between said internal memory means and said external memory in coordination with communication processes being conducted in said synchronous section relative to respective network channels.
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Abstract
A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device can handle multiple channels of voice and varied protocol data traffic, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous special purpose logic sections in the device respectively interface with the network and a bus extending to external processing systems. Logic in the synchronous section forms plural-stage receive and transmit processing pipelines relative to the network interface. A "resource manager" element (RSM) and time swap (TS) RAM memory operate to dynamically vary states in these pipelines in synchronism with channel time slots at the network interface, whereby each pipeline operates in multitasking mode to perform plural functions relative to each channel during each time slot. The device also includes integrated memory queues in which communication data and channel status information are stacked relative to the device interfaces. Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while supporting operations in the synchronous section pipelines so that critical time dependencies between consecutive pipeline stages, and between the pipelines and external processors, are lessened.
104 Citations
55 Claims
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1. A data link control device, for connection between a data communication network and a parallel information transfer bus, said network having multiple data communication channels for concurrent communication of data signals relative to terminals remote from said device, said device having multiple internal channels, associatable with said network channels, for processing data signals in transit between respective said network channels and said parallel bus, said bus connectable to an external data processing system and to an external memory associated with said system, said device thereby interfacing between said network and both said external system and external memory, via said bus, said device comprising:
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logic circuits partitioned into synchronous and asynchronous circuit sections;
circuits in said synchronous section operating in time division multiplex, in cyclically recurrent time slots assignable to said internal channels of said device, for transferring data signals between said network channels and said internal device channels;
said asynchronous section operating to transfer data signals between internal device channels and said external memory in asynchronous relation to occurrences of time slots assigned to respective internal channels in the synchronous section;internal memory means connected to both said synchronous and asynchronous circuit sections for storing communication data signals in transit between said synchronous and asynchronous sections relative to said internal channels; said synchronous section processing data signals in said internal channels in transit between respective said network channels and said internal memory means, and conducting said processing in synchronous relation to times of occurrence of respective said time division time slots assigned to respective internal channels in said synchronous section;
said asynchronous section directing transfers of said data signals between said internal memory means and said external memory, via said bus, said data signals being transferred relative to respective said internal channels but in asynchronous time relation to times of recurrence of time slots assigned in said synchronous section to respective internal channels; andcoordinating means interfacing between said synchronous and asynchronous sections, for instigating transfers of data signals relative to said internal channels by said asynchronous section, between said internal memory means and external memory, in response to request signals from said synchronous section, said coordinating means thereby instigating asynchronous transfers of data signals relative to said internal channels, between said internal memory means and said external memory in coordination with communication processes being conducted in said synchronous section relative to respective network channels. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 55)
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37. A data link control device, for connection between a data communication network having multiple channels of data signal communication and a parallel information transfer bus which connects to one or more external data processing systems and to one or more external memories associated with said systems, said device comprising:
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synchronous and asynchronous sections of special purpose logic circuits, circuits in said synchronous section interfacing between said network and circuits in said asynchronous section for processing data received from and transmitted to said network in cyclically recurrent time division slots, said time slots being assignable to multiple diversely configurable internal communication channels maintainable within both said synchronous and asynchronous sections of said device;
said internal channels being associatable with said network channels;
said circuits in said synchronous section operating in synchronism with said time slots to process data relative to internal channels associated with respective slots;internal memory means coupled to circuits in both said sections, said internal memory means having storage spaces associated with individual said internal channels;
the space associated with each said internal channel being sufficient to store plural bytes of communication data in transit relative to the respective internal channel;said circuits in said synchronous section performing processing tasks on communication data in transit relative to said network channels through respective said internal channels within said synchronous section, and connecting to said internal memory means for transferring communication data between said internal channels within said synchronous section and respective storage spaces in said internal memory means; circuits in said asynchronous section interfacing between said internal memory means and said bus, and operating in asynchronous relation to said time slots in said synchronous section for transferring said communication data relative to respective said internal channels between respective said storage spaces in said internal memory means and a said external memory via said bus, said asynchronous section being capable of operating relative to any said storage space in said internal memory means to transfer plural bytes of data at one time between that space and said external memory; and means interfacing between said circuits in said synchronous and asynchronous sections for coordinating operations of said synchronous and asynchronous sections relative to said internal channels and storage spaces in said internal memory means associated with respective channels, whereby a coordinated flow of communication data is maintained between said internal memory means and said external memory relative to each internal channel that is currently active so as to minimize possibilities for underrun or overrun errors to occur relative to respective internal channels. - View Dependent Claims (38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52)
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53. In a data processing system containing a host processor and addressable system memory connected by a bus, said bus being connectable to plural devices and subject to control by said host processor and said devices for transferring information between said host processor, said system memory and said devices, a subsystem representing one of said plural devices, said subsystem having plural internal channels for managing the flow of data between said system memory and a plurality of peripheral devices, said subsystem including a plurality of circuits for performing various operations relative to said internal channels, said plurality of circuits including a DMA control circuit for directing data transfer operations relative to said system memory via said bus, said subsystem comprising:
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bus control circuit means connected between said subsystem DMA control circuit and said bus for competitively controlling access to said bus and cooperating with said DMA control circuit, when access to said bus is so controlled, for accessing said system memory in a direct access mode; said DMA control circuit operating relative to said bus control circuit means to supply address signals to said bus control circuit means representing addresses in said system memory; a local random access memory (RAM) having portions of its addressable storage capacity assigned to said internal channels for storing data in transit between said system memory and said peripheral devices via said internal channels and said bus, said local RAM having other portions of its said capacity assigned relative to said internal channels for storing processing state control information defining instantaneous processing states of said subsystem relative to said internal channels; and means coupling said DMA control circuit to said local RAM for enabling said DMA control circuit to operate in an asynchronous manner relative to said internal channels and said peripheral devices while transferring data relative to said internal channels, between storage spaces assigned to said internal channels in both said local RAM and said system memory. - View Dependent Claims (54)
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Specification