All-digital quadrature modulator

• US 5,121,412 A
• Filed: 01/03/1989
• Issued: 06/09/1992
• Est. Priority Date: 01/03/1989
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Borth, David E.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US07/292,719
• Time in Patent Office: 1,253 Days
• Field of Search: 375/67, 375/56, 375/45, 375/47, 375/52, 375/77, 375/39, 375/58, 375/61, 375/62, 332/100, 332/103, 332/106, 332/104
• US Class Current: 375/308
• CPC Class Codes: H04L 27/2007 in which the phase change within each symbol period is constrained coset coding H04L27/186
• CPC Class Codes: H04L 27/2092 with digital generation of the modulated carrier (does not include the modulation of a digitally generated carrier)

Abstract

A CPFSK quadrature modulator (300) is disclosed utilizing an all-digital implementation. The serial data input signal (20 ) is formatted into parallel overlapping bits using a shift register (202), an up/down counter (206), and an interpolation counter (204) and applied as address lines to in-phase and quadrature-phase memories (208, 210). A multiple of the bit clock is used to address carrier generation ROMs (216, 218). The carrier signal is then modulated by the in-phase and quadrature-phase data signals (212, 214, 222), converted to an analog signal by a D/A converter (250), and low pass filtered (254) to generate the analog output signal (255). A single ROM (440) is utilized to implement all the look-up tables, multipliers, and adder. The all-digital implementation allows for precise control of the modulation index to h═0.5±0.05 percent over time, temperature, power levels, etc.

Claims

1. A digital modulator for generating a quadrature modulated signal, said modulator comprising:

first means for formatting an input data signal into a digital representation of in-phase (I) and quadrature-phase (Q) data signals, including first memory means for storing data and for providing said digital representation of said in-phase (I) and said quadrature-phase (Q) data signals in response to said input data signal;

means for providing a digital carrier signal representative of an integer multiple of a bit clock signal;

second means for formatting said digital carrier signal into a digital representation of in-phase (I) and quadrature-phase (Q) carrier signals, including second memory means for storing data and for providing said digital representation of said in-phase (I) and said quadrature-phase (Q) carrier signals in response to said digital carrier signal;

means, including said second memory means, for storing a digital representation of a quadrature modulated signal, and for providing said digital representation of said quadrature modulated signal in response to said in-phase (I) and quadrature-phase (Q) data signals and said in-phase (I) and quadrature-phase (Q) carrier signals; and

means for converting said digital representation of said quadrature modulated signal into an analog output signal having a precise modulation index.

2. The modulator according to claim 1, wherein the functions of said first and second formatting means are performed using entirely digital electronic circuitry.

3. The modulator according to claim 1, wherein said first formatting means includes means for translating serial input data into parallel input data.

4. The modulator according to claim 1, wherein said second formatting means includes

means for providing a digital carrier signal representative of an integer multiple of said bit clock signal.

5. The modulator according to claim 1, wherein said modulator generates a continuous-phase frequency-shift keyed (CPFSK) signal.

6. The modulator according to claim 5, wherein said modulation index is 0.5±

0.05%.

7. The modulator according to claim 1, wherein said modulator generates a Gaussian minimum shift keyed (GMSK) signal.

8. A digital quadrature modulator for generating a continuous-phase frequency-shift keyed (CPFSK) signal, said modulator comprising:

means for translating serial input data having a predetermined bit rate into parallel input data;

means for determining the phase quadrant of said serial input data in response to said bit rate and said parallel input data, thereby providing a phase control signal;

means for interpolating between data bits of said serial input data, thereby providing an interpolation signal; and

memory means for providing a digital representation of a CPFSK signal in response to said parallel input data, said phase control signal, and said interpolation signal.

9. The modulator according to claim 8, wherein said translating means includes an L-bit serial-to-parallel shift register into which said serial input data signal is clocked at a bit rate 1/T, thereby generating an L-bit parallel representation of said serial input data signal.

10. The modulator according to claim 9, wherein said phase quadrant determining means includes a 2-bit up/down binary counter, wherein the up/down counter control is determined by the most-significant output bit of said shift register, and wherein said up/down counter is clocked at the bit rate 1/T.

11. The modulator according to claim 8, wherein said interpolating means includes a log₂ M-bit binary counter clocked at M times the bit rate 1/T, thereby providing a parallel data word corresponding to the binary state of said log₂ M-bit counter.

12. The modulator according to claim 8, wherein said memory means is a single read-only memory (ROM) addressed by said parallel input data, said phase control signal, and said interpolation signal.

13. The modulator according to claim 8, wherein said memory means provides a CPFSK signal with a modulation index of 0.5 at a carrier frequency of J/MT, wherein 1/T is the bit rate, wherein J<

M/2and wherein J and M are integers.

14. The modulator according to claim 8, further comprising means for converting said digital representation of said CPFSK signal into an analog CPFSK signal.

15. The modulator according to claim 14, wherein said converting means includes a digital-to-analog converter which provides an analog sampled data signal clocked at M times the bit rate 1/T, wherein M is an integer.

16. The modulator according to claim 14, wherein said converting means includes a filter to select the desired spectral replica from said analog sampled data signal, thereby providing said analog CPFSK signal.

17. A digital modulator for generating a quadrature modulated signal, said modulator comprising:

first means for transforming a serial data signal into a parallel data signal including first memory means for storing data and providing a digital representation of in-phase (I) and quadrature-phase (Q) data signals in response to said serial data signal;

means for providing a radio frequency (RF) carrier signal representative of an integer multiple of a bit clock signal;

second means for transforming said radio frequency (RF) carrier signal into a digital carrier signal including second memory means for storing data and for providing a digital representation of in-phase (I) and quadrature-phase (Q) carrier signals in response to said digital carrier signal;

means, including said second memory means, for digitally modulating said digital representation of I and Q carrier signals with said digital representation of I and Q data signals, thereby providing a digital representation of a quadrature modulated signal; and

means for converting said digital representation of said quadrature modulated signal into an analog output signal having a precise modulation index, whereby digital-to-analog conversion is performed subsequent to quadrature modulation.

18. The modulator according to claim 17, wherein the functions of said modulating means is performed using entirely digital electronic circuitry.

19. The modulator according to claim 17, wherein the functions of said first and second transforming means are performed using entirely digital electronic circuitry.

20. The modulator according to claim 17, wherein said first transforming means includes

means for translating serial input data into parallel input data.

21. The modulator according to claim 17, wherein said modulator generates a continuous-phase frequency-shift keyed (CPFSK) signal.

22. The modulator according to claim 21, wherein said modulation index is 0.5±

0.05%.

23. A means for generating an analog continuous-phase frequency-shift keyed (CPFSK) signal s(t) by quadrature modulating a radio frequency (RF) carrier f_c with an input signal d(t) utilizing entirely digital circuitry, comprising:

means for providing a data vector d of length L in response to d(t), wherein d has a bit rate 1/T;

means for determining a phase parameter of d(t) in response to d , thereby providing a phase signal θ

(t,d );

means for providing an interpolation signal having a clock rate M/T;

memory means for providing a digital output signal s(t,d ) when addressed with d and said interpolation signal, where

space="preserve" listing-type="equation">s(t,d )=A cos [ω

.sub.c t+θ

(t,d )],

and where A=amplitude, and ω

_c =2π

f_c ; and

means for converting s(t,d ) into s(t).

24. The CPFSK signal generating means according to claim 23, wherein said memory means includes pre-stored instantaneous values of s(t,d ).

25. The CPFSK signal generating means according to claim 23, wherein said phase parameter determining means includes means for determining the phase quadrant of d(t) in response to d , thereby providing phase signal ψ

(t,d ), wherein said memory means is further addressed with said phase signal ψ

(t,d ), and wherein ##EQU12## where h is the modulation index, and q(t) is the modulation phase pulse signal.

26. A digital quadrature modulator for generating a continuous-phase frequency-shift keyed (CPFSK) signal having a modulation index of 0.5 comprising:

a formatting circuit comprising;

an L-bit serial-to-parallel shift register into which a serial data signal is clocked at a bit rate 1/T, and which generates an L-bit parallel data signal representative of said serial data signal;

a 2-bit up/down binary counter, clocked at the bit rate 1/T, having its up/down counter control determined by the most significant bit of said parallel data signal, thereby providing a 2-bit phase state signal;

a log₂ M-bit counter, clocked at M times the bit rate 1/T, which generates a log₂ M-bit data interpolation signal representative of the binary state of said log₂ M-bit counter;

a memory circuit comprising;

a memory device having B2.sup.(L+log.sbsp.2^M+2) storage locations, having address lines coupled to said parallel data signal, said phase state signal, and said data interpolation signal, having a B-bit output, and having stored therein representations of CPFSK signal data with a modulation index of 0.5 at a carrier frequency of J/MT where J<

M/2, and J and M are integers.

27. The digital quadrature modulator according to claim 26, further comprising a digital-to-analog converter circuit which converts said B-bit CPFSK signal data into analog sampled-data representations of a CPFSK signal clocked at M times the bit rate 1/T.

28. The digital quadrature modulator according to claim 26, further comprising a filter circuit which selects the desired spectral replica of analog signals output from said converter circuit, thereby providing a CPFSK signal having a modulation index of 0.5 having a tolerance within ±

0.05%.

29. A method for generating a continuous-phase frequency-shift keyed (CPFSK) signal by quadrature modulating a radio frequency (RF) carrier with a digital input signal utilizing entirely digital techniques, said method comprising the steps of:

translating serial input data having a predetermined bit rate into parallel input data;

determining the phase quadrant of said serial input data in response to said bit rate and said parallel input data, thereby providing a phase control signal;

interpolating between data bits of said serial input data, thereby providing an interpolation signal;

addressing a memory utilizing said parallel input data, said phase control signal, and said interpolation signal;

outputting a digital representation of a CPFSK signal from said memory; and

converting said digital representation into an analog CPFSK output signal having a precise modulation index.

30. The method according to claim 29, wherein said translating step includes clocking said serial input data signal into an L-bit serial-to-parallel shift register at a bit rate 1/T, thereby generating an L-bit parallel representation of said serial input data signal.

31. The method according to claim 30, wherein said phase quadrant determining step includes clocking a 2-bit up/down binary counter at the bit rate 1/T, wherein the up/down counter control is determined by the most-significant output bit of said shift register.

32. The method according to claim 29, wherein said interpolating step includes clocking a log₂ M-bit binary counter at M times the bit rate 1/T, thereby providing a parallel data word corresponding to the binary state of said log₂ M-bit counter.

33. The method according to claim 29, wherein said memory means outputs a CPFSK signal with a modulation index of 0.5 at a carrier frequency of J/MT, wherein 1/T is the bit rate, wherein J<

M/2, and wherein J and M are integers.

34. A method for generating a continuous-phase frequency-shift keyed (CPFSK) signal s(t) by a quadrature modulating a radio frequency (RF) carrier f_c with a digital input signal d(t) utilizing entirely digital techniques, said method comprising the steps of:

(a) providing a data vector d of length L in response to d(t), wherein d has a bit rate 1/T;

(b) determining a phase parameter of d(t) in response to d , thereby providing a phase signal θ

(t,d );

(c) providing an interpolation signal having a clock rate M/T;

(d) addressing a digital memory with d , θ

(t,d ) and said interpolation signal; and

(e) outputting s(t,d ) from said digital memory, wherein

space="preserve" listing-type="equation">s(t,d )=A cos [ω

.sub.c t+θ

(t,d )]

and wherein A=amplitude and ω

_c =2π

f_c.

35. The method according to claim 34, further comprising the step of converting the digital signal s(t,d ) into an analog signal s(t).

36. The method according to claim 34, wherein said digital memory includes pre-stored instantaneous values of s(t,d ).

37. The method according to claim 34, wherein step (b) includes the step of determining the phase quadrant of d(t) in response to d , thereby providing phase signal ψ

(t,d ).

38. The method according to claim 37, wherein ##EQU13## where h is the modulation index, and q(t) is the modulation phase pulse signal.

39. A method for modulating a radio frequency carrier f_c with a digital input signal d(t), said method comprising the steps of:

(a) providing a data vector d of length L in response to d(t), wherein d has a bit rate 1/T;

(b) determining the phase quadrant of d(t) in response to d , thereby providing a phase signal ψ

(t,d );

(c) providing an interpolation signal having a clock rate M/T;

(d) calculating parameters s(t,d ) of s(t) according to the equation

space="preserve" listing-type="equation">s(t,d )=A cos (ω

.sub.c t+θ

(t,d )),

where ##EQU14## and where A=amplitude, ω

_c =2π

f_c, h is the modulation index, and q(t) is the modulation phase pulse signal;

(e) storing parameters s(t,d ) into a digital memory at address locations determined by d , ψ

(t,d ), and said interpolation signal; and

(f) generating a modulated analog signal responsive to said stored parameters s(t,d ).

40. The method according to claim 39, wherein step (d) further comprises the steps of:

(1) generating a first quadrature signal I(t) in accordance with the equation I(t)=cos [θ

(t,d )];

(2) generating a second quadrature signal Q(t) in accordance with the equation Q(t)=sin [θ

(t,d )];

(3) generating modulated signal I_mod (t) by multiplying T(t) by cos[ω

_c (t)];

(4) generating modulated signal Q_mod (t) by multiplying Q(t) by sin[ω

_c (t)]; and

(5) generating s(t,d ) by subtracting Q_mod (t) from I_mod (t).

41. A method for quadrature modulation of a radio frequency (RF) carrier f_c with an input signal d(t), said method comprising the steps of:

(a) sampling the input signal d(t) at a sample rate 1/T, thereby creating a sampled data signal d(n) of length L;

(b) defining parameters of a first signal I(t,d(n)) from said sampled data signal d(n);

(c) defining parameters of a second signal Q(t,d(n)) from said sampled data signal d(n), wherein Q(t,d(n)) is in phase quadrature with I(t,d(n));

calculating parameters of modulated signal Imod(t,d(n)) by multiplying I(t,d(n)) by cos(.sup.ω

.sbsp.c (t)), where .sup.ω

.sbsp.c =2π

f_c ;

(e) calculating parameters of modulated signal Qmod.sup.(t,d(n)) by multiplying Q(t,d(n)) by sin(.sup.ω

.sbsp.c (t));

(f) calculating parameters of a continuous-phase frequency shift keyed (CPFSK) signal s(t,d(n)) by subtracting Qmod.sup.(t,d(n)) from Imod .sup.(t,d(n)) ;

(g) storing parameters of said CPFSK signal s(t,d(n)) into a digital memory; and

(h) generating an analog signal responsive to said stored parameters of said CPFSK signal s(t,d(n)).

42. A radio transmitter comprising:

means for providing a bit clock signal having a predetermined bit rate;

means for providing serial input data having said bit rate;

means for translating said serial input data into parallel input data;

first memory means for storing data and for providing a digital representation of in-phase (I) and quadrature-phase (Q) component data signals in response to said parallel input data;

means for providing a digital carrier signal representative of an integer multiple of said bit clock signal;

second memory means for storing data and for providing a digital representation of in-phase (I) and quadrature-phase (Q) component carrier signals in response to said digital carrier signal;

means, including said second memory means, for digitally modulating said I and Q carrier signals by said I and Q data signals, said second memory means further comprising means for storing data and for providing said digital quadrature modulating signal in response to said I and Q carrier signals and said I and Q data signals, thereby providing I and Q digital component signals;

means, including said second memory means, for combining said I and Q digital component signals, thereby providing a digital quadrature modulated signal;

means for converting said digital quadrature modulated signal into an analog output signal; and

means for transmitting said analog output signal.

43. The transmitter according to claim 42, further comprising:

means for determining the phase quadrant of said serial input data in response to said bit rate and said parallel input data, thereby providing a phase control signal; and

means for interpolating between data bits of said serial input data in response to said bit rate, thereby providing an interpolation signal.

44. The transmitter according to claim 43, wherein said second memory is addressed by said interpolation signal.

45. The transmitter according to claim 43, wherein said first and second memories are addressed by said parallel input data, said phase control signal, and said interpolation signal.

46. The transmitter according to claim 42, wherein said quadrature modulated signal is a continuous-phase frequency-shift keyed (CPFSK) signal.

47. The transmitter according to claim 46, wherein said analog output signal has a modulation index equal to 0.5±

0.05%.

48. The transmitter according to claim 42, wherein said quadrature modulated signal is a Gaussian minimum shift keyed (GMSK) signal.