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Double DRAM cell

  • US 5,122,476 A
  • Filed: 05/20/1991
  • Issued: 06/16/1992
  • Est. Priority Date: 01/28/1991
  • Status: Expired due to Term
First Claim
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1. A process for forming a double DRAM cell comprising:

  • forming a first transistor (T1) on an active area of a silicon substrate by doping the active area with a source and a drain, forming a gate oxide over the active area and then forming an isolated word line (WL1) over the active area;

    forming a first storage capacitor (C1) to the transistor (T1);

    depositing an insulating layer on the first transistor (T1) to form a first cell including the first access transistor (T1) and the storage capacitor C1;

    opening a seed contact through the insulating layer to the drain, or source of the first transistor (T1);

    forming an intermediate substrate of monocrystalline silicon by selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) from the seed contact by;

    a. depositing a thick sacrificial layer over the insulating oxide layer;

    b. planarizing the sacrificial layer to form a planarized sacrificial block;

    c. depositing an oxide layer over the sacrificial block and forming an opening to the sacrificial block;

    d. etching away the sacrificial block utilizing the opening to form a cavity; and

    e. epitaxially growing a monocrystalline silicon within the cavity to form the intermediate substrate,forming a second transistor (T2) on the intermediate substrate by doping the intermediate substrate to form an active area, forming a source and a drain, forming a gate oxide over the active area and then forming an isolated word line (WL2) over the active area of the intermediate substrate;

    forming an insulated bit line to the drain of the second transistor (T2) as a common contact between the first (T1) and second (T2) transistor which are connected by the location of the seed contact; and

    forming a second storage capacitor (C2) for the second transistor (T2) to form a second cell including the second access transistor (T2) and second storage capacitor (C2).

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