Capacitive position detector

• US 5,122,755 A
• Filed: 05/02/1991
• Issued: 06/16/1992
• Est. Priority Date: 05/11/1990
• Status: Expired due to Term

• Current Assignee: BEI Sensors & Systems Company Incorporated (Schneider Electric SE)
• Original Assignee: New SD, Inc.
• Inventors: Nootbaar, Michael W., Newell, Gerald R.
• Primary Examiner(s): Harvey, Jack B.
• Application Number:
  US07/697,926
• Time in Patent Office: 411 Days
• Field of Search: 324/602, 324/605, 324/660, 324/661, 324/678, 324/681, 340/870.37
• US Class Current: 324/678
• CPC Class Codes: G01D 5/2417 by varying separation

Abstract

A differential capacitive pickoff detector circuit for measuring the difference in spacing of a pair of differential pickoff capacitor plates. Current sources are provided for each output terminal of each of the pair of differential capacitors so that for each capacitor output terminal a current signal alternates between a first current level and a second current level at a predetermined carrier clock switching rate. The capacitors are varied to provide DSB-LC voltage signals across each of the capacitors. The average value of each of the alternating voltages and their amplitudes are automatically adjusted to predetermined levels. The two DSB-LC voltage signals are combined to provide a DSB-SC signal. The DSB-SC signal is synchronously demodulated using a quadrature reference carrier clock signal to provide an output baseband signal which represents the difference between the spacing of the first and second differential capacitor plates.

Claims

1. A differential capacitive pickoff detector circuit for measuring the difference in capacitance between a first differential capacitor and a second differential capacitor, said first differential capacitor having a first terminal connected to a first reference potential and having a second terminal, said second differential capacitor having a first terminal connected to said first reference potential and having a second terminal, comprising:

first current source means, coupled to said second terminal of said first differential capacitor, for providing a first alternating current signal to said first capacitor, said first current signal alternating between a first current level and a second current level at a predetermined switching rate, said first alternating current signal producing a first voltage signal at said second terminal of said first differential capacitor, said first capacitor adapted to being varied to provide a first double-sideband, large-carrier, amplitude-modulated DSB-LC voltage signal at said second terminal;

first means for adjusting the average value of said first voltage signal at said second terminal of said first differential capacitor to a predetermined level;

second current source means, coupled to said second terminal of said second differential capacitor, for providing a second alternating current signal to said second capacitor, said second current signal alternating between a first current level and a second current level at the predetermined switching rate in synchronism with said first alternating current signal, said second alternating current signal producing a second voltage signal at said second terminal of said second differential capacitor, said second capacitor adapted to being varied to provide a second double-sideband, large carrier, amplitude-modulated DSB-LC voltage signal at said second terminal of said second differential capacitor;

second means for adjusting the average value of said second voltage signal at said second terminal to a predetermined level;

combining means for synchronously combining said first DSB-LC voltage signal with said second DSB-LC voltage signal to provide an amplitude-modulated double-sideband, suppressed-carrier DSB-SC signal;

means for synchronously demodulating said DSB-SC signal using a reference carrier clock signal to provide an output difference signal which represents the difference between the capacitance values of said first and said second differential capacitors.

2. The circuit of claim 1 wherein said first current source means comprises:

a first current generator providing a current I to said second terminal of said first differential capacitor;

first switch means for intermittently connecting a second current generator to said second terminal of said first differential capacitor to provide a current -2I to said second terminal of said first differential capacitor;

a third current generator providing a current I to the second terminal of said second differential capacitor;

second switch means for intermittently connecting a fourth current generator to said second terminal of said second differential capacitor to provide a current -2I to said second terminal of said second differential capacitor.

3. The circuit of claim 2 wherein said first switch means includes means for alternately intermittently connecting said second current generator and said fourth current generator to said second terminal of said first differential capacitor, and wherein said second switch means includes means for alternately intermittently connecting said fourth current generator and said second current generator to said second terminal of said second differential capacitor.

4. The circuit of claim 1 wherein said first means for adjusting the average value of said first voltage signal includes:

(a) a first lowpass filter, which has an input terminal connected to said second terminal of said first differential capacitor and which has an output terminal for providing a first low-frequency control signal proportional to the average value of the voltage level of said second terminal of said first differential capacitor;

(b) means for controlling said first alternating current signal with said first low-frequency control signal; and

wherein said second means for adjusting the average value of said second voltage signal includes;

(a) a second lowpass filter, which has an input terminal connected to said second terminal of said second differential capacitor and which has an output terminal for providing a second low-frequency control signal proportional to the average value of the voltage level of said second terminal of said second differential capacitor;

(b) means for controlling said second alternating current signal with said second low-frequency control signal.

5. The circuit of claim 1 wherein said combining means includes a difference circuit for taking the difference between the first DSB-LC voltage signal and the second DSB-LC voltage signal.

6. The circuit of claim 5 wherein the difference circuit includes:

first means for converting said first DSB-LC voltage signal to a corresponding current signal;

second means for converting said second DSB-LC voltage signal to a corresponding current signal; and

difference means for combining said corresponding current signals to provide a difference signal current.

7. The circuit of claim 6 wherein said first and said second means for converting includes a common impedance element.

8. The circuit of claim 7 wherein said difference circuit includes a first transistor having base, emitter, and collector terminals, said base terminal being coupled to said second terminal of said first differential capacitor, said emitter terminal being coupled to a first difference-circuit current source;

a second transistor having base, emitter, and collector terminals, said base terminal being coupled to said second terminal of said second differential capacitor, said emitter terminal being coupled to a second difference-current source; and

wherein said common impedance element includes a resistor having a first terminal coupled to the emitter terminal of said first transistor and having a second terminal coupled to the emitter terminal of said second transistor, wherein the signal current through said resistor is proportional to the difference between said first DSB-LC voltage signal and said second DSB-LC voltage signal.

9. The circuit of claim 8 wherein said collector terminal of said first transistor is coupled to a reference input terminal of a first current-mirror circuit and wherein said collector terminal of said second transistor is coupled to a reference input terminal of a second current-mirror circuit;

including a third current-mirror circuit having a reference input terminal to which is coupled the output current of the first current-mirror circuit, wherein the output terminal of said third current-mirror is coupled to the output terminal of said second current-mirror circuit so that the output current of the second current-mirror circuit and the output current of the third current-mirror circuit buck to provide an output current proportional to the difference between the first DSB-LC voltage signal and the second DSB-LC voltage signal.

10. The circuit of claim 1 wherein the means for synchronously demodulating includes:

an input terminal for receiving a current DSB-SC signal;

a load impedance having a first terminal and a second terminal;

first switch means for coupling said input terminal to said first terminal of the load impedance;

second switch means for coupling said second terminal of said load impedance to a reference voltage, wherein said first and said second switch means are controlled by one phase of the reference carrier clock signal to be simultaneously open and by the other phase of the reference carrier clock signal to be simultaneously closed;

third switch means for coupling said input terminal to said second terminal of the load impedance;

fourth switch means for coupling said first terminal of said load impedance to a reference voltage, wherein said third and said fourth switch means are controlled by the other phase of the reference carrier clock signal to be simultaneously open and by the one phase of the reference carrier clock to be simultaneously closed;

whereby the DSB-SC signal is synchronously demodulated to provide a demodulated signal across said load impedance.

11. The circuit of claim 10 wherein said load impedance includes an integrating capacitance for integrating said demodulated signal.

12. The circuit of claim 10 including difference means for providing a difference signal proportional to the difference between the voltages on said first and said second terminals of said load impedance;

means for providing a half-difference signal equal to one-half of the difference signal to said first terminal of the load impedance capacitor through said fourth switch means;

means for providing an inverted half-difference signal to said second terminal of the load impedance capacitor through said second switch means;

whereby the difference signal is provided with smooth signal transitions when said first and second switch means and said third and said fourth switch means are opened and closed by the reference carrier clock signal.

13. The circuit of claim 1 including means for maintaining the peak-to-peak level of said DSB-LC voltage signals at a predetermined average value.

14. A modulator for encoding the capacitance of a variable capacitor, said capacitor having a first terminal connected to a first reference potential and having a second terminal, comprising:

first current source means, coupled to said second terminal of said capacitor, for providing an alternating current signal to said capacitor, said current signal alternating between a first current level and a second current level at a predetermined switching rate, said alternating current signal producing a voltage signal at said second terminal of said capacitor, said capacitor adapted to being varied to provide a double-sideband, large-carrier amplitude-modulated DSB-LC voltage signal at said second terminal;

first current source means comprising a current generator providing a current I to said second terminal of said capacitor; and

switch means for intermittently connecting a second current generator to said second terminal of said capacitor to provide a current -2I to said second terminal of said capacitor.

15. The modulator of claim 14 including means for adjusting the average value of said voltage signal at said second terminal to a predetermined level.

16. The modulator of claim 15 wherein said means for adjusting the average value of said voltage signal includes:

a lowpass filter, which has an input terminal connected to said second terminal of said capacitor and which has an output terminal for providing a low-frequency control signal proportional to the average value of the voltage level of said second terminal of said capacitor; and

means for controlling said alternating current signal with said first low-frequency control signal.

17. A differential capacitive pickoff modulator circuit for encoding the difference in capacitance between a first differential capacitor and a second differential capacitor, said first differential capacitor having a first terminal connected to a first reference potential and having a second terminal, said second differential capacitor having a first terminal connected to said first reference potential and having a second terminal, comprising:

first current source means, coupled to said second terminal of said first differential capacitor, for providing a first alternating current signal to said first capacitor, said first current signal alternating between a first current level and a second current level at a predetermined switching rate, said first alternating current signal producing a first voltage signal at said second terminal of said first differential capacitor, said first capacitor adapted to being varied to provide a first double-sideband, large-carrier amplitude-modulated DSB-LC voltage signal at said second terminal;

second current source means, coupled to said second terminal of said second differential capacitor, for providing a second alternating current signal to said second capacitor, said second current signal alternating between a first current level and a second current level at the predetermined switching rate in synchronism with said first alternating current signal, said second alternating current signal producing a second voltage signal at said second terminal of said second differential capacitor, said second capacitor adapted to being varied to provide a second double-sideband, large-carrier amplitude-modulated DSB-LC voltage signal at said second terminal.

18. The circuit of claim 17 including:

first means for adjusting the average value of said first voltage signal at said second terminal to a predetermined level; and

second means for adjusting the average value of said second voltage signal at said second terminal to a predetermined level.

19. The circuit of claim 17 wherein said first current source means comprises:

a first current generator providing a current I to said second terminal of said first differential capacitor;

first switch means for intermittently connecting a second current generator to said second terminal of said first differential capacitor to provide a current -2I to said second terminal of said first differential capacitor;

a third current generator providing a current I to the second terminal of said second differential capacitor;

second switch means for intermittently connecting a fourth current generator to said second terminal of said second differential capacitor to provide a current -2I to said second terminal of said second differential capacitor.

20. The circuit of claim 19 wherein said first switch means includes means for alternately intermittently connecting said second current generator and said fourth current generator to said second terminal of said first differential capacitor, and wherein said second switch means includes means for alternately intermittently connecting said fourth current generator and said second current generator to said second terminal of said second differential capacitor.

21. The circuit of claim 18 wherein said first means for adjusting the average value of said first voltage signal includes:

a first lowpass filter, which has an input terminal connected to said second terminal of said first differential capacitor and which has an output terminal for providing a first low-frequency control signal proportional to the average value of the voltage level of said second terminal of said first differential capacitor;

means for controlling said first alternating current signal with said first low-frequency control signal; and

wherein said second means for adjusting the average value of said second voltage signal includes;

a second lowpass filter, which has an input terminal connected to said second terminal of said second differential capacitor and which has an output terminal for providing a second low-frequency control signal proportional to the average value of the voltage level of said second terminal of said second differential capacitor;

means for controlling said second alternating current signal with said second low-frequency control signal.

22. The circuit of claim 17 including combining means for synchronously combining said first DSB-LC voltage signal with said second DSB-LC voltage signal to provide an amplitude-modulated double-sideband, suppressed-carrier DSB-SC signal.

23. The circuit of claim 22 wherein said combining means includes a difference circuit for taking the difference between the first DSB-LC voltage signal and the second DSB-LC voltage signal.

24. The circuit of claim 23 wherein the difference circuit includes:

means for converting said first DSB-LC voltage signal and said second DSB-LC voltage signal to respective current signals; and

difference means for combining said respective current signals to provide a difference signal current.

25. The circuit of claim 23 wherein said means for converting includes a common impedance element.

26. The circuit of claim 25 wherein said differential circuit includes a first transistor having base, emitter, and collector terminals, said base terminal being coupled to said second terminal of said first differential capacitor, said emitter terminal being coupled to a first difference-circuit current source;

a second transistor having base, emitter, and collector terminals, said base terminal being coupled to said second terminal of said second differential capacitor, said emitter terminal being coupled to a second difference-current source; and

a resistor having a first terminal coupled to the emitter terminal of said first transistor and having a second terminal coupled to the emitter terminal of said second transistor, wherein the signal current through said resistor is proportional to the difference between said first DSB-LC voltage signal and said second DSB-LC voltage signal.

27. The circuit of claim 26 wherein said collector terminal of said first transistor is coupled to a reference input terminal of a first current-mirror circuit and wherein said collector terminal of said second transistor is coupled to a reference input terminal of a second current-mirror circuit;

and

including a third current-mirror circuit having a reference input terminal to which is coupled the output current of the first current-mirror circuit, wherein the output terminal of said third current-mirror is coupled to the output terminal of said second current-mirror circuit so that the output current of the second current-mirror circuit and the output current of the third current-mirror circuit buck to provide an output current proportional to the difference between the first DSB-LC voltage signal and the second DSB-LC voltage signal.

28. The circuit of claim 17 including means for maintaining the peak-to-peak level of said DSB-LC voltage signals at a predetermined average value.

29. A circuit for synchronously demodulating a double-sideband, suppressed-carrier DSB-SC signal comprising:

an input terminal for receiving a current DSB-SC signal;

a load impedance having a first terminal and a second terminal;

first switch means for coupling said input terminal to said first terminal of the load impedance;

second switch means for coupling said second terminal of said load impedance to a reference voltage, wherein said first and said second switch means are controlled by one phase of the reference carrier clock signal to be simultaneously open and by the other phase of the reference carrier clock signal to be simultaneously closed;

third switch means for coupling said input terminal to said second terminal of the load impedance;

fourth switch means for coupling said first terminal of said load impedance to a reference voltage, wherein said third and said fourth switch means are controlled by the other phase of the reference carrier clock signal to be simultaneously open and by the one phase of the reference carrier clock to be simultaneously closed; and

whereby the DSB-SC signal is synchronously demodulated to provide a demodulated signal across said load impedance.

30. The circuit of claim 29 wherein said load impedance includes an integrating capacitance for integrating said demodulated signal.

31. The circuit of claim 29 including difference means for providing a difference signal proportional to the difference between the voltages on said first and said second terminals of said load impedance;

means for providing a half-difference signal equal to one-half of the difference signal to said first terminal of the load impedance capacitor through said fourth switch means;

means for providing an inverted half-difference signal to said second terminal of the load impedance capacitor through said second switch means; and

whereby the difference signal is provided with smooth signal transitions when said first and second switch means and said third and said fourth switch means are opened and closed by the reference carrier clock signal.

32. In a circuit for monitoring a difference in capacitance between first and second differential capacitors:

means for producing a double sideband, large carrier, amplitude modulated signal on each of the capacitors, means for synchronously combining the double sideband, large carrier signals to provide a double sideband, suppressed carrier signal, and means for synchronously demodulating the double sideband suppressed carrier signal.

33. The circuit of claim 32 wherein the means for producing a double sideband, large carrier, amplitude modulated signal on each of the capacitors includes means for alternately applying currents having levels of I and -2I to the capacitors.

34. The circuit of claim 32 including means for adjusting the signal on each of the capacitors to a predetermined average voltage level.

35. The circuit of claim 34 wherein the means for adjusting the signal on each of the capacitors comprises a lowpass filter coupled to the capacitor for providing a low frequency control signal corresponding to the average voltage level of the signal on the capacitor, and means responsive to the control signal for controlling the current applied to the capacitor.

36. The circuit of claim 32 including means for maintaining the signal on each of the capacitors at a predetermined peak-to-peak voltage.

37. The circuit of claim 36 wherein the means for maintaining the signal on each of the capacitors at a predetermined peak-to-peak voltage includes means for providing a summation signal corresponding to the sum of the signals on the capacitors, means for monitoring the summation signal and providing a peak signal corresponding to the peak amplitude of the summation signal, and means responsive to the peak signal for adjusting the current applied to the capacitors.

38. The circuit of claim 32 wherein the means for synchronously combining the signals on the capacitors includes a load impedance, means responsive to a reference clock signal for applying the signal from the first capacitor to the load impedance during a first phase of the reference clock signal, and means responsive to the reference clock signal for applying the signal from the second capacitor to the load impedance during a second phase of the reference clock signal.