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Capacitive position detector

  • US 5,122,755 A
  • Filed: 05/02/1991
  • Issued: 06/16/1992
  • Est. Priority Date: 05/11/1990
  • Status: Expired due to Term
First Claim
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1. A differential capacitive pickoff detector circuit for measuring the difference in capacitance between a first differential capacitor and a second differential capacitor, said first differential capacitor having a first terminal connected to a first reference potential and having a second terminal, said second differential capacitor having a first terminal connected to said first reference potential and having a second terminal, comprising:

  • first current source means, coupled to said second terminal of said first differential capacitor, for providing a first alternating current signal to said first capacitor, said first current signal alternating between a first current level and a second current level at a predetermined switching rate, said first alternating current signal producing a first voltage signal at said second terminal of said first differential capacitor, said first capacitor adapted to being varied to provide a first double-sideband, large-carrier, amplitude-modulated DSB-LC voltage signal at said second terminal;

    first means for adjusting the average value of said first voltage signal at said second terminal of said first differential capacitor to a predetermined level;

    second current source means, coupled to said second terminal of said second differential capacitor, for providing a second alternating current signal to said second capacitor, said second current signal alternating between a first current level and a second current level at the predetermined switching rate in synchronism with said first alternating current signal, said second alternating current signal producing a second voltage signal at said second terminal of said second differential capacitor, said second capacitor adapted to being varied to provide a second double-sideband, large carrier, amplitude-modulated DSB-LC voltage signal at said second terminal of said second differential capacitor;

    second means for adjusting the average value of said second voltage signal at said second terminal to a predetermined level;

    combining means for synchronously combining said first DSB-LC voltage signal with said second DSB-LC voltage signal to provide an amplitude-modulated double-sideband, suppressed-carrier DSB-SC signal;

    means for synchronously demodulating said DSB-SC signal using a reference carrier clock signal to provide an output difference signal which represents the difference between the capacitance values of said first and said second differential capacitors.

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