Bistable logic device using trench transistors
First Claim
1. A bi-stable logic device comprising:
- a first doped region having a first conductivity type formed in the surface of a substrate having a second conductivity type;
a second doped region having said first conductivity type formed in said surface of said substrate, said second doped region being separate from said first doped region;
a first buried doped region having said first conductivity type formed in said substrate below said surface, said first buried doped region being separate from said first and second doped regions, said first buried doped region being connected to a first reference potential;
a second buried doped region having said first conductivity type formed in said substrate below said surface, said second buried doped region being separate from said first, second and first buried doped regions, said second buried doped region being connected to a second reference potential;
a first trench formed in said substrate extending from said first doped region to said first buried doped region;
a first gate formed in said first trench, said first gate controlling conductivity between said first and first buried doped regions;
a second trench formed in said substrate extending from said first doped region to said second buried doped region;
a second gate formed in said second trench, said second gate controlling the conductivity of said substrate between said first doped region and said second buried doped region;
a third trench formed in said substrate extending from said second doped region to said first buried doped region;
a third gate formed in said third trench, said third gate controlling the conductivity of said substrate between said second doped region and said first buried doped region;
a fourth trench formed in said substrate, said fourth trench extending from said second doped region to said second buried doped region;
a fourth gate formed in said fourth trench, said fourth gate controlling the conductivity of said substrate between said second and said second buried doped regions;
a first conductor electrically connecting said first and fourth gates to said second doped region; and
a second conductor electrically connecting said second and third gates to said first doped region.
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Abstract
The described embodiments of the present invention show a structure and process for fabricating this structure in which a bi-stable logic device, such as a static random access memory cell, is formed. The advantages of the described embodiments are most particularly found when in an array. In two parrallel lines formed in buried diffusions beneath the surface of the integrated circuit, Vdd or the power supply voltage and ground are alternately provided. Two vertical transistors control conduction between ground and a surface diffusion are formed being connected to the buried ground diffusion. Two additional transistors are formed as load devices connected between the surface diffusion and the Vdd buried diffusion. The surface diffusion is connected to complementary bit lines via access transistors formed connecting the surface diffusion to contact points for the complementary bit lines. By using buried ground and supply lines, large space savings may be obtained with the present memory cell. In addition, because of the vertical structure of all devices inthe memory cell, increased soft error immunity is obtained. Further space savings are achieved by the use of local interconnect processing for forming interconnections between surface devices in the cells. In another embodiment, a buried diffusion is used as an interconnection node for a bi-stable device using vertical devices.
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Citations
58 Claims
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1. A bi-stable logic device comprising:
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a first doped region having a first conductivity type formed in the surface of a substrate having a second conductivity type; a second doped region having said first conductivity type formed in said surface of said substrate, said second doped region being separate from said first doped region; a first buried doped region having said first conductivity type formed in said substrate below said surface, said first buried doped region being separate from said first and second doped regions, said first buried doped region being connected to a first reference potential; a second buried doped region having said first conductivity type formed in said substrate below said surface, said second buried doped region being separate from said first, second and first buried doped regions, said second buried doped region being connected to a second reference potential; a first trench formed in said substrate extending from said first doped region to said first buried doped region; a first gate formed in said first trench, said first gate controlling conductivity between said first and first buried doped regions; a second trench formed in said substrate extending from said first doped region to said second buried doped region; a second gate formed in said second trench, said second gate controlling the conductivity of said substrate between said first doped region and said second buried doped region; a third trench formed in said substrate extending from said second doped region to said first buried doped region; a third gate formed in said third trench, said third gate controlling the conductivity of said substrate between said second doped region and said first buried doped region; a fourth trench formed in said substrate, said fourth trench extending from said second doped region to said second buried doped region; a fourth gate formed in said fourth trench, said fourth gate controlling the conductivity of said substrate between said second and said second buried doped regions; a first conductor electrically connecting said first and fourth gates to said second doped region; and a second conductor electrically connecting said second and third gates to said first doped region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A bi-stable logic device comprising:
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a first doped region having a first conductivity type formed in the surface of a substrate having a second conductivity type; a second doped region having said first conductivity type formed in said surface of said substrate, said second doped region being separate from said first doped region; a first buried doped region having said first conductivity type formed in said substrate below said surface, said first buried doped region being separate from said first and second doped regions, said first buried doped region being connected to a first reference potential; a second buried doped region having said first conductivity type formed in said substrate below said surface, said fourth doped region being separate from said first, second and first buried doped regions, said second buried doped region being connected to a second reference potential; a first trench formed in said substrate in said first area and extending from said first doped region to said first buried doped region; a first gate formed in said first trench, said first gate controlling conductivity between said first and first buried doped regions; a second trench formed in said substrate extending to said second buried doped region; a first resistor formed in said second trench, said first resistor providing a resistive connection to said second buried doped region; a third trench formed in said substrate extending from said second doped region to said first buried doped region; a second gate formed in said third trench, said second gate controlling the conductivity of said substrate between said second doped region and said first buried doped region; a fourth trench formed in said substrate, said fourth trench extending to said second buried doped region; a second resistor formed in said fourth trench, said second resistor providing resistive connection to said second buried doped regions; a first conductor electrically connecting said first gate and said first resistor to said second doped region; and a second conductor electrically connecting said second gate and said second resistor to said first doped region. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A bi-stable logic device comprising:
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a first doped region having a first conductivity type formed in the surface of a substrate having a second conductivity type; a second doped region having said first conductivity type formed in said surface of said substrate, said second doped region being separate from said first doped region; a first buried doped region having said first conductivity type formed in said substrate below said surface, said first buried doped region being separate from said first and second doped regions, said first buried doped region being connected to a first reference potential; a second buried doped region having said first conductivity type formed in said substrate below said surface, said second buried doped region being separate from said first, second and first buried doped regions, said second buried doped region being connected to a second reference potential; a first trench formed in said substrate extending from said first doped region to said first buried doped region; a first gate formed in said first trench, said first gate controlling conductivity between said first and first buried doped regions; a second trench formed in said substrate extending from said first doped region to said second buried doped region; a first channel layer formed in said second trench connected at one end to said first doped region and at the other end to said second buried doped region; a second gate formed in said second trench and over said first channel layer, said second gate controlling the conductivity of said first channel layer; a third trench formed in said substrate extending from said second doped region to said first buried doped region; a third gate formed in said third trench, said third gate controlling the conductivity of said substrate between said second doped region and said first buried doped region; a fourth trench formed in said substrate, said fourth trench extending from said second doped region to said second buried doped region; a second channel layer formed in said fourth trench connected at one end to said second doped region and a the other end to said second buried doped region; a fourth gate formed in said fourth trench and over said second channel layer, said fourth gate controlling the conductivity of said second channel layer; a first conductor electrically connecting said first and second gates to said second doped region; and a second conductor electrically connecting said third and fourth gates to said first doped region. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A random access memory device comprising:
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a plurality of memory cells arranged in a regular array, each cell comprising; a first doped region having a first conductivity type formed in the surface of a substrate having a second conductivity type; a second doped region having said first conductivity type formed in said surface of said substrate, said second doped region being separate from said first doped region; a first buried doped region having said first conductivity type formed in said substrate below said surface, said first buried doped region being separate from said first and second doped regions, said first buried doped region being connected to a first reference potential; a second buried doped region having said first conductivity type formed in said substrate below said surface, said second buried doped region being separate from said first, second and first buried doped regions, said second buried doped region being connected to a second reference potential; a first trench formed in said substrate extending from said first doped region to said first buried doped region; a first gate formed in said first trench, said first gate controlling conductivity between said first and first buried doped regions; a second trench formed in said substrate extending from said first doped region to said second buried doped region; a second gate formed in said second trench, said second gate controlling the conductivity of said substrate between said first doped region and said second buried doped region; a third trench formed in said substrate extending from said second doped region to said first buried doped region; a third gate formed in said third trench, said third gate controlling the conductivity of said substrate between said second doped region and said first buried doped region; a fourth trench formed in said substrate extending from said second doped region to said second buried doped region; a fourth gate formed in said fourth trench, said fourth gate controlling the conductivity of said substrate between said second and said second buried doped regions; a first conductor electrically connecting said first and fourth gates to said second doped region; and a second conductor electrically connecting said second and third gates to said first doped region; wherein said first and second buried doped regions extend the width of said array. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38)
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39. A bistable logic circuit, comprising:
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a first buried doped region of a first conductivity type formed in a substrate of a second conductivity type, said first buried doped region being spaced from a surface of said substrate; a second buried doped region of said first conductivity type formed in said substrate, said second buried doped region being spaced from said surface of said substrate; a first vertical transistor located having a first current handling terminal connected to said first buried doped region, a second current handling terminal extending to said surface of said substrate, said second current handling terminal being connected to a first reference potential, and a control terminal controlling current between said first and second current handling terminals, said control terminal being connected to said second buried doped region; a second vertical transistor located having a first current handling terminal connected to said second buried doped region, a second current handling terminal extending to said surface of said substrate, said second current handling terminal being connected to said first reference potential, and a control terminal controlling current between said first and second current handling terminals, said control terminal being connected to said first buried doped region; a first load device extending between a first terminal connected to said first buried doped region and a second terminal at said surface and said second terminal being connected to a second reference potential; and a second load device extending between a first terminal connected to said second buried doped region and a second terminal at said surface and said second terminal being connected to said second reference potential. - View Dependent Claims (40, 41, 42, 43, 44, 45)
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46. A random access memory device comprising:
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a plurality of bitlines formed on a substrate, said bitlines running substantially parallel to one another; a plurality of memory cells each of said memory cell being connected to two bitlines and one wordline, and each of said memory cells comprising; a first buried doped region of a first conductivity type formed in a substrate of a second conductivity type, said first buried doped region being spaced from a surface of said substrate; a second buried doped region of said first conductivity type formed in said substrate, said second buried doped region being spaced from said surface of said substrate; a first vertical transistor having a first current handling terminal connected to said first buried doped region, a second current handling terminal extending to said surface of said substrate, said second current handling terminal being connected to a first reference potential, and a control terminal controlling current between said first and second current handling terminals, said control terminal being connected to said second buried doped region; a second vertical transistor having a first current handling terminal connected to said second buried doped region, a second current handling terminal extending to said surface of said substrate, said second current handling terminal being connected to said first reference potential, and a control terminal controlling current between said first and second current handling terminals, said control terminal being connected to said first buried doped region; a first load device having a first terminal connected to said first buried doped region and a second terminal extending to said surface and said second terminal being connected to a second reference potential; a second load device having a first terminal connected to said second buried doped region and a second terminal extending to said surface and said second surface terminal being connected to said second reference potential; a first vertical access transistor having a first current handling terminal connected to said first buried doped region, a second current handling terminal connected to one of said two bitlines and a control terminal connected to said wordline; and a second vertical access transistor having a first current handling terminal connected to said second buried doped region, a second current handling terminal connected to the other of said two bitlines and a control terminal connected to said wordline. - View Dependent Claims (47, 48, 49, 50)
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51. A bistable logic device comprising:
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a first buried doped region of a first conductivity type formed in a substrate of a second conductivity type, said first buried doped region being spaced from a surface of said substrate; a second buried doped region of said first conductivity type formed in said substrate, said second buried doped region being spaced from said surface of said substrate; a first transistor formed in a trench formed in said substrate extending to said first buried doped region, a gate insulating layer formed on the surfaces of said trench, a doped drain region formed in said substrate at said surface adjacent to said trench, said doped drain region being connected to a first reference potential, a gate formed in said trench on said insulating layer, said gate being electrically connected to said second buried doped region; a second transistor formed in a trench formed in said substrate extending to said second buried doped region, a gate insulating layer formed on the surfaces of said trench, a doped drain region formed in said substrate at said surface adjacent to said trench, said doped drain region being connected to a first reference potential, a gate formed in said trench on said insulating layer, said gate being electrically connected to said first buried doped region; a first load device formed in a trench extending from said surface to said first buried doped region, an insulating layer formed on the sidewalls of said trench and resistive material formed in said trench being connected to a second reference potential at said surface; and a second load device formed in a trench extending from said surface to said second buried doped region, an insulating layer formed on the sidewalls of said trench and resistive material formed in said trench being connected to said second reference potential at said surface. - View Dependent Claims (52, 53, 54, 55)
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56. A random access memory device comprising:
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a plurality of bitlines formed on a substrate, said bitlines running substantially parallel to one another; a plurality of wordlines running substantially parallel to said bitlines; and a plurality of memory cells each of said memory cells being connected to two bitlines and one wordline, and each of said memory cells comprising; a first buried doped region of a first conductivity type formed in a substrate of a second conductivity type, said first buried doped region being spaced from a surface of said substrate; a second buried doped region of said first conductivity type formed in said substrate, said second buried doped region being spaced from said surface of said substrate;
a first transistor formed in a trench formed in said substrate extending to said first buried doped region, a gate insulating layer formed on the surfaces of said trench, a doped drain region formed in said substrate at said surface adjacent to said trench, said doped drain region being connected to a first reference potential, a gate formed in said trench on said insulating layer, said gate being electrically connected to said second buried doped region;a second transistor formed in a trench formed in said substrate extending to said second buried doped region, a gate insulating layer formed on the surfaces of said trench, a doped drain region formed in said substrate at said surface adjacent to said trench, said doped drain region being connected to a first reference potential, a gate formed in aid trench on said insulating layer, said gate being electrically connected to said first buried doped region;
a first load device formed in a trench extending from said surface to said first buried doped region, an insulating layer formed on the sidewalls of said trench and resistive material formed in said trench being connected to a second reference potential at said surface;a second load device formed in a trench extending from said surface to said second buried doped region, an insulating layer formed on the sidewalls of said trench and resistive material formed in said trench being connected to said second reference potential at said surface; a first access transistor formed in a trench extending from said surface to said first buried doped region, a gate insulating layer formed on the surfaces of said trench, a doped drain region formed in said substrate at said surface adjacent to said trench, said doped drain region being connected to one of said two bitlines, and a gate formed on said gate insulating layer connected to said wordline; and a second access transistor formed in a trench extending from said surface to said second buried doped region, a gate insulating layer formed on the surfaces of said trench, a doped drain region formed in said substrate at said surface adjacent to said trench said doped drain region being connected to one of said two bitlines and a gate formed on said gate insulating layer being connected to said wordline. - View Dependent Claims (57, 58)
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Specification