Bistable logic device using trench transistors

• US 5,122,846 A
• Filed: 03/26/1991
• Issued: 06/16/1992
• Est. Priority Date: 01/25/1990
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Haken, Roger A.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US07/675,237
• Time in Patent Office: 448 Days
• Field of Search: 357/23.4, 357/23.6, 357/41, 357/42, 357/45, 357/55
• US Class Current: 257/66
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/15 comprising a resistor load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors

Abstract

The described embodiments of the present invention show a structure and process for fabricating this structure in which a bi-stable logic device, such as a static random access memory cell, is formed. The advantages of the described embodiments are most particularly found when in an array. In two parrallel lines formed in buried diffusions beneath the surface of the integrated circuit, V_dd or the power supply voltage and ground are alternately provided. Two vertical transistors control conduction between ground and a surface diffusion are formed being connected to the buried ground diffusion. Two additional transistors are formed as load devices connected between the surface diffusion and the V_dd buried diffusion. The surface diffusion is connected to complementary bit lines via access transistors formed connecting the surface diffusion to contact points for the complementary bit lines. By using buried ground and supply lines, large space savings may be obtained with the present memory cell. In addition, because of the vertical structure of all devices inthe memory cell, increased soft error immunity is obtained. Further space savings are achieved by the use of local interconnect processing for forming interconnections between surface devices in the cells. In another embodiment, a buried diffusion is used as an interconnection node for a bi-stable device using vertical devices.

Claims

1. A bi-stable logic device comprising:

a first doped region having a first conductivity type formed in the surface of a substrate having a second conductivity type;

a second doped region having said first conductivity type formed in said surface of said substrate, said second doped region being separate from said first doped region;

a first buried doped region having said first conductivity type formed in said substrate below said surface, said first buried doped region being separate from said first and second doped regions, said first buried doped region being connected to a first reference potential;

a second buried doped region having said first conductivity type formed in said substrate below said surface, said second buried doped region being separate from said first, second and first buried doped regions, said second buried doped region being connected to a second reference potential;

a first trench formed in said substrate extending from said first doped region to said first buried doped region;

a first gate formed in said first trench, said first gate controlling conductivity between said first and first buried doped regions;

a second trench formed in said substrate extending from said first doped region to said second buried doped region;

a second gate formed in said second trench, said second gate controlling the conductivity of said substrate between said first doped region and said second buried doped region;

a third trench formed in said substrate extending from said second doped region to said first buried doped region;

a third gate formed in said third trench, said third gate controlling the conductivity of said substrate between said second doped region and said first buried doped region;

a fourth trench formed in said substrate, said fourth trench extending from said second doped region to said second buried doped region;

a fourth gate formed in said fourth trench, said fourth gate controlling the conductivity of said substrate between said second and said second buried doped regions;

a first conductor electrically connecting said first and fourth gates to said second doped region; and

a second conductor electrically connecting said second and third gates to said first doped region.

2. A device as in claim 1 further comprising:

a fifth doped region having said first conductivity type formed in said substrate, said fifth doped region being separate from said first doped region and defining a first channel region;

a fifth gate formed on the surface of said substrate controlling the conductivity of said first channel region;

a sixth doped region having said first conductivity type formed in said substrate, said fifth doped region being separate from said second doped region and defining a second channel region; and

a sixth gate formed on the surface of said substrate controlling the conductivity of said second channel region.

3. A device as in claim 1 wherein said substrate comprises crystalline silicon.

4. A device as in claim 2 wherein said substrate comprises crystalline silicon.

5. A device as in claim 2 wherein said fifth and sixth gates are electrically connected.

6. A device as in claim 1 wherein said first, second, third and fourth gates comprise polycrystalline silicon.

7. A device as in claim 2 wherein said first, second, third, fourth, fifth and sixth gates comprise polycrystalline silicon.

8. A device as in claim 1 wherein said first, second, third and fourth gates comprise polycrystalline silicon on a dielectric layer.

9. A device as in claim 2 wherein said first, second, third, fourth, fifth and sixth gates comprise polycrystalline silicon on a dielectric layer.

10. A bi-stable logic device comprising:

a first doped region having a first conductivity type formed in the surface of a substrate having a second conductivity type;

a second doped region having said first conductivity type formed in said surface of said substrate, said second doped region being separate from said first doped region;

a first buried doped region having said first conductivity type formed in said substrate below said surface, said first buried doped region being separate from said first and second doped regions, said first buried doped region being connected to a first reference potential;

a second buried doped region having said first conductivity type formed in said substrate below said surface, said fourth doped region being separate from said first, second and first buried doped regions, said second buried doped region being connected to a second reference potential;

a first trench formed in said substrate in said first area and extending from said first doped region to said first buried doped region;

a first gate formed in said first trench, said first gate controlling conductivity between said first and first buried doped regions;

a second trench formed in said substrate extending to said second buried doped region;

a first resistor formed in said second trench, said first resistor providing a resistive connection to said second buried doped region;

a third trench formed in said substrate extending from said second doped region to said first buried doped region;

a second gate formed in said third trench, said second gate controlling the conductivity of said substrate between said second doped region and said first buried doped region;

a fourth trench formed in said substrate, said fourth trench extending to said second buried doped region;

a second resistor formed in said fourth trench, said second resistor providing resistive connection to said second buried doped regions;

a first conductor electrically connecting said first gate and said first resistor to said second doped region; and

a second conductor electrically connecting said second gate and said second resistor to said first doped region.

11. A device as in claim 10 further comprising:

a fifth doped region having said first conductivity type formed in said substrate, said fifth doped region being separate from said first doped region and defining a first channel region;

a fifth gate formed on the surface of said substrate controlling the conductivity of said first channel region;

a sixth doped region having said first conductivity type formed in said substrate, said fifth doped region being separate from said second doped region and defining a second channel region; and

a sixth gate formed on the surface of said substrate controlling the conductivity of said second channel region.

12. A device as in claim 10 wherein said substrate comprises crystalline silicon.

13. A device as in claim 11 wherein said substrate comprises crystalline silicon.

14. A device as in claim 11 wherein said fifth and sixth gates are electrically connected.

15. A device as in claim 10 wherein said first and second gates, and said first and second resistors comprise polycrystalline silicon.

16. A device as in claim 11 wherein said first, second, fifth and sixth gates, and said first and second resistors comprise polycrystalline silicon.

17. A device as in claim 10 wherein said first and second gates comprise polycrystalline silicon on a dielectric layer.

18. A device as in claim 11 wherein said first, second, fifth and sixth gates comprise polycrystalline silicon on a dielectric layer.

19. A bi-stable logic device comprising:

a first doped region having a first conductivity type formed in the surface of a substrate having a second conductivity type;

a second doped region having said first conductivity type formed in said surface of said substrate, said second doped region being separate from said first doped region;

a first buried doped region having said first conductivity type formed in said substrate below said surface, said first buried doped region being separate from said first and second doped regions, said first buried doped region being connected to a first reference potential;

a second buried doped region having said first conductivity type formed in said substrate below said surface, said second buried doped region being separate from said first, second and first buried doped regions, said second buried doped region being connected to a second reference potential;

a first trench formed in said substrate extending from said first doped region to said first buried doped region;

a first gate formed in said first trench, said first gate controlling conductivity between said first and first buried doped regions;

a second trench formed in said substrate extending from said first doped region to said second buried doped region;

a first channel layer formed in said second trench connected at one end to said first doped region and at the other end to said second buried doped region;

a second gate formed in said second trench and over said first channel layer, said second gate controlling the conductivity of said first channel layer;

a third trench formed in said substrate extending from said second doped region to said first buried doped region;

a third gate formed in said third trench, said third gate controlling the conductivity of said substrate between said second doped region and said first buried doped region;

a fourth trench formed in said substrate, said fourth trench extending from said second doped region to said second buried doped region;

a second channel layer formed in said fourth trench connected at one end to said second doped region and a the other end to said second buried doped region;

a fourth gate formed in said fourth trench and over said second channel layer, said fourth gate controlling the conductivity of said second channel layer;

a first conductor electrically connecting said first and second gates to said second doped region; and

a second conductor electrically connecting said third and fourth gates to said first doped region.

20. A device as in claim 19 wherein said first channel layer and said second channel layer comprise polycrystalline silicon.

21. A device as in claim 19 further comprising:

a fifth doped region having said first conductivity type formed in said substrate, said fifth doped region being separate from said first doped region and defining a first channel region;

a fifth gate formed on the surface of said substrate controlling the conductivity of said first channel region;

a sixth doped region having said first conductivity type formed in said substrate, said fifth doped region being separate from said second doped region and defining a second channel region; and

a sixth gate formed on the surface of said substrate controlling the conductivity of said second channel region.

22. A device as in claim 19 wherein said substrate comprises crystalline silicon.

23. A device as in claim 21 wherein said first channel layer and said second channel layer comprise polycrystalline silicon.

24. A device as in claim 21 wherein said substrate comprises crystalline silicon.

25. A device as in claim 21 wherein said fifth and sixth gates are electrically connected.

26. A device as in claim 19 wherein said first, second, third and fourth gates comprise polycrystalline silicon.

27. A device as in claim 21 wherein said first, second, third, fourth, fifth and sixth gates comprise polycrystalline silicon.

28. A device as in claim 19 wherein said first, second, third and fourth gates comprise polycrystalline silicon on a dielectric layer.

29. A device as in claim 21 wherein said first, second, third, fourth, fifth and sixth gates comprise polycrystalline silicon on a dielectric layer.

30. A random access memory device comprising:

a plurality of memory cells arranged in a regular array, each cell comprising;

a first doped region having a first conductivity type formed in the surface of a substrate having a second conductivity type;

a second doped region having said first conductivity type formed in said surface of said substrate, said second doped region being separate from said first doped region;

a first buried doped region having said first conductivity type formed in said substrate below said surface, said first buried doped region being separate from said first and second doped regions, said first buried doped region being connected to a first reference potential;

a second buried doped region having said first conductivity type formed in said substrate below said surface, said second buried doped region being separate from said first, second and first buried doped regions, said second buried doped region being connected to a second reference potential;

a first trench formed in said substrate extending from said first doped region to said first buried doped region;

a first gate formed in said first trench, said first gate controlling conductivity between said first and first buried doped regions;

a second trench formed in said substrate extending from said first doped region to said second buried doped region;

a second gate formed in said second trench, said second gate controlling the conductivity of said substrate between said first doped region and said second buried doped region;

a third trench formed in said substrate extending from said second doped region to said first buried doped region;

a third gate formed in said third trench, said third gate controlling the conductivity of said substrate between said second doped region and said first buried doped region;

a fourth trench formed in said substrate extending from said second doped region to said second buried doped region;

a fourth gate formed in said fourth trench, said fourth gate controlling the conductivity of said substrate between said second and said second buried doped regions;

a first conductor electrically connecting said first and fourth gates to said second doped region; and

a second conductor electrically connecting said second and third gates to said first doped region;

wherein said first and second buried doped regions extend the width of said array.

31. A device as in claim 30, each cell further comprising:

a fifth doped region having said first conductivity type formed, said fifth doped region being separate from said first doped region and defining a first channel region;

a fifth gate formed on the surface of said substrate controlling the conductivity of said first channel region;

a sixth doped region having said first conductivity type formed, said fifth doped region being separate from said second doped region and defining a second channel region; and

a sixth gate formed on the surface of said substrate controlling the conductivity of said second channel region.

32. A device as in claim 30 wherein said substrate comprises crystalline silicon.

33. A device as in claim 31 wherein said substrate comprises crystalline silicon.

34. A device as in claim 31 wherein said fifth and sixth gates are electrically connected by a conductive word line extending the width of the array.

35. A device as in claim 30 wherein said first, second, third and fourth gates comprise polycrystalline silicon.

36. A device as in claim 31 wherein said first, second, third, fourth, fifth and sixth gates comprise polycrystalline silicon.

37. A device as in claim 30 wherein said first, second, third and fourth gates comprise polycrystalline silicon on a dielectric layer.

38. A device as in claim 31 wherein said first, second, third, fourth, fifth and sixth gates comprise polycrystalline silicon on a dielectric layer.

39. A bistable logic circuit, comprising:

a first buried doped region of a first conductivity type formed in a substrate of a second conductivity type, said first buried doped region being spaced from a surface of said substrate;

a second buried doped region of said first conductivity type formed in said substrate, said second buried doped region being spaced from said surface of said substrate;

a first vertical transistor located having a first current handling terminal connected to said first buried doped region, a second current handling terminal extending to said surface of said substrate, said second current handling terminal being connected to a first reference potential, and a control terminal controlling current between said first and second current handling terminals, said control terminal being connected to said second buried doped region;

a second vertical transistor located having a first current handling terminal connected to said second buried doped region, a second current handling terminal extending to said surface of said substrate, said second current handling terminal being connected to said first reference potential, and a control terminal controlling current between said first and second current handling terminals, said control terminal being connected to said first buried doped region;

a first load device extending between a first terminal connected to said first buried doped region and a second terminal at said surface and said second terminal being connected to a second reference potential; and

a second load device extending between a first terminal connected to said second buried doped region and a second terminal at said surface and said second terminal being connected to said second reference potential.

40. A device as in claim 39 further comprising:

a first vertical access transistor having a first current handling terminal connected to said second buried doped region, a second current handling terminal serving as a second output terminal and a control terminal for receiving a second control access signal.

41. A device as in claim 40 wherein said first control access signal and said second control access signal are the same signal.

42. A device as in claim 39 wherein said first and second load devices comprise resistors.

43. A device as in claim 39 wherein said first and second load devices comprise field effect transistors.

44. A device as in claim 39 wherein said first and second load devices comprise field effect transistors having opposite conductivity type to said first and second transistors.

45. A device as in claim 39 wherein said first and second load devices comprise field effect transistors having a channel region in a polycrytalline layer.

46. A random access memory device comprising:

a plurality of bitlines formed on a substrate, said bitlines running substantially parallel to one another;

a plurality of memory cells each of said memory cell being connected to two bitlines and one wordline, and each of said memory cells comprising;

a first buried doped region of a first conductivity type formed in a substrate of a second conductivity type, said first buried doped region being spaced from a surface of said substrate;

a second buried doped region of said first conductivity type formed in said substrate, said second buried doped region being spaced from said surface of said substrate;

a first vertical transistor having a first current handling terminal connected to said first buried doped region, a second current handling terminal extending to said surface of said substrate, said second current handling terminal being connected to a first reference potential, and a control terminal controlling current between said first and second current handling terminals, said control terminal being connected to said second buried doped region;

a second vertical transistor having a first current handling terminal connected to said second buried doped region, a second current handling terminal extending to said surface of said substrate, said second current handling terminal being connected to said first reference potential, and a control terminal controlling current between said first and second current handling terminals, said control terminal being connected to said first buried doped region;

a first load device having a first terminal connected to said first buried doped region and a second terminal extending to said surface and said second terminal being connected to a second reference potential;

a second load device having a first terminal connected to said second buried doped region and a second terminal extending to said surface and said second surface terminal being connected to said second reference potential;

a first vertical access transistor having a first current handling terminal connected to said first buried doped region, a second current handling terminal connected to one of said two bitlines and a control terminal connected to said wordline; and

a second vertical access transistor having a first current handling terminal connected to said second buried doped region, a second current handling terminal connected to the other of said two bitlines and a control terminal connected to said wordline.

47. A device as in claim 46 wherein said first and second load devices comprise resistors.

48. A device as in claim 46 wherein said first and second load devices comprise field effect transistors.

49. A device as in claim 46 wherein said first and second load devices comprise field effect transistors having opposite conductivity type to said first and second transistors.

50. A device as in claim 46 wherein said first and second load devices comprise field effect transistors having a channel region in a polycrytalline silicon layer.

51. A bistable logic device comprising:

a first buried doped region of a first conductivity type formed in a substrate of a second conductivity type, said first buried doped region being spaced from a surface of said substrate;

a second buried doped region of said first conductivity type formed in said substrate, said second buried doped region being spaced from said surface of said substrate;

a first transistor formed in a trench formed in said substrate extending to said first buried doped region, a gate insulating layer formed on the surfaces of said trench, a doped drain region formed in said substrate at said surface adjacent to said trench, said doped drain region being connected to a first reference potential, a gate formed in said trench on said insulating layer, said gate being electrically connected to said second buried doped region;

a second transistor formed in a trench formed in said substrate extending to said second buried doped region, a gate insulating layer formed on the surfaces of said trench, a doped drain region formed in said substrate at said surface adjacent to said trench, said doped drain region being connected to a first reference potential, a gate formed in said trench on said insulating layer, said gate being electrically connected to said first buried doped region;

a first load device formed in a trench extending from said surface to said first buried doped region, an insulating layer formed on the sidewalls of said trench and resistive material formed in said trench being connected to a second reference potential at said surface; and

a second load device formed in a trench extending from said surface to said second buried doped region, an insulating layer formed on the sidewalls of said trench and resistive material formed in said trench being connected to said second reference potential at said surface.

52. A device as in claim 51 wherein said resistive material is undoped polycrystalline silicon.

53. A device as in claim 51 wherein

said connection from said gate of said first transistor to said second buried doped region comprises a trench extending from said surface to said second buried doped region, an insulating layer formed on the sidewalls of said trench, conductive material filling the remainder of said trench and a conductor extending from said conductive material at the top of said trench to said gate of said first transistor;

and

said connection from said gate of said second transistor to said first buried doped region comprises a trench extending from said surface to said second buried doped region, an insulating layer formed on the sidewalls of said trench, conductive material filling the remainder of said trench and a conductor extending from said conductive material at the top of said trench to said gate of said second first transistor.

54. A device as in claim 51 further comprising:

a first access transistor formed in a trench extending from said surface to said first buried doped region, a gate insulating layer formed on the surfaces of said trench, a doped drain region formed in said substrate at said surface adjacent to said trench, said doped drain region serving as a first output terminal and a gate formed on said gate insulating layer serving as a control terminal for receiving a first control access signal;

a second access transistor formed in a trench extending from said surface to said second buried doped region, a gate insulating layer formed on the surfaces of said trench, a doped drain region formed in said substrate at said surface adjacent to said trench, said doped drain region serving as a second output terminal and a gate formed on said gate insulating layer serving as a control terminal for receiving a second control access signal.

55. A device as in claim 54 wherein said first control access signal and said second control access signal are the same signal.

56. A random access memory device comprising:

a plurality of bitlines formed on a substrate, said bitlines running substantially parallel to one another;

a plurality of wordlines running substantially parallel to said bitlines; and

a plurality of memory cells each of said memory cells being connected to two bitlines and one wordline, and each of said memory cells comprising;

a first buried doped region of a first conductivity type formed in a substrate of a second conductivity type, said first buried doped region being spaced from a surface of said substrate;

a second buried doped region of said first conductivity type formed in said substrate, said second buried doped region being spaced from said surface of said substrate;

a first transistor formed in a trench formed in said substrate extending to said first buried doped region, a gate insulating layer formed on the surfaces of said trench, a doped drain region formed in said substrate at said surface adjacent to said trench, said doped drain region being connected to a first reference potential, a gate formed in said trench on said insulating layer, said gate being electrically connected to said second buried doped region;

a second transistor formed in a trench formed in said substrate extending to said second buried doped region, a gate insulating layer formed on the surfaces of said trench, a doped drain region formed in said substrate at said surface adjacent to said trench, said doped drain region being connected to a first reference potential, a gate formed in aid trench on said insulating layer, said gate being electrically connected to said first buried doped region;

a first load device formed in a trench extending from said surface to said first buried doped region, an insulating layer formed on the sidewalls of said trench and resistive material formed in said trench being connected to a second reference potential at said surface;

a second load device formed in a trench extending from said surface to said second buried doped region, an insulating layer formed on the sidewalls of said trench and resistive material formed in said trench being connected to said second reference potential at said surface;

a first access transistor formed in a trench extending from said surface to said first buried doped region, a gate insulating layer formed on the surfaces of said trench, a doped drain region formed in said substrate at said surface adjacent to said trench, said doped drain region being connected to one of said two bitlines, and a gate formed on said gate insulating layer connected to said wordline; and

a second access transistor formed in a trench extending from said surface to said second buried doped region, a gate insulating layer formed on the surfaces of said trench, a doped drain region formed in said substrate at said surface adjacent to said trench said doped drain region being connected to one of said two bitlines and a gate formed on said gate insulating layer being connected to said wordline.

57. A device as in claim 56 wherein said resistive material is undoped polycrystalline silicon.

58. A device as in claim 56 wherein

said connection from said gate of said first transistor to said second buried doped region comprises a trench extending from said surface to said second buried doped region, an insulating layer formed on the sidewalls of said trench, conductive material filling the remainder of said trench and a conductor extending from said conductive material at the top of said trench to said gate of said first transistor;

and

said connection from said gate of said second transistor to said first buried doped region comprises a trench extending from said surface to said second buried doped region, an insulating layer formed on the sidewalls of said trench, conductive material filling the remainder of said trench and a conductor extending from said conductive material at the top of said trench to said gate of said second first transistor.