Data stream smoothing using a FIFO memory

• US 5,122,988 A
• Filed: 07/17/1991
• Issued: 06/16/1992
• Est. Priority Date: 09/21/1989
• Status: Expired due to Term

• Current Assignee: Xcerra Corporation (COHU Incorporated)
• Original Assignee: Schlumberger Technologies Incorporated (Schlumberger NV)
• Inventors: Graeve, Egbert
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US07/732,351
• Time in Patent Office: 335 Days
• Field of Search: 365/219, 365/221, 365/222, 365/230.08
• US Class Current: 365/219
• CPC Class Codes: G01R 31/31919 Storing and outputting test patterns G01R31/31924 takes precedence; arithmetic and random test patterns generator
• CPC Class Codes: G06F 5/14 for overflow or underflow handling, e.g. full or empty flags
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles

Abstract

A data stream smoothing circuit wherein a FIFO memory receives data from the DRAM, and a memory status circuit provides a memory-full status signal when the FIFO memory contains a selected amount of data from the DRAM. A refresh timer generates a refresh request signal whenever DRAM refresh should be performed. When the refresh request signal is generated, a refresh control circuit refreshes a row of data in the DRAM upon occurrence of the next memory-full status signal.

Claims

1. A data communicating circuit for providing a continuous stream of data from a DRAM which is periodically refreshed by a refresh circuit comprising:

a FIFO memory;

DRAM communicating means, coupled to the DRAM and to the FIFO memory, for communicating data from the DRAM to the FIFO memory;

memory status means, associated with the FIFO memory, for providing a memory full signal when the FIFO memory contains a selected amount of data from the DRAM;

refresh means, coupled to the DRAM, for refreshing the DRAM, the refresh means comprising;

a refresh timer for providing a refresh due signal at fixed periodic time intervals;

a refresh counter for sequentially providing DRAM row address values; and

refresh control means, coupled to the refresh timer, to the refresh counter, and to the memory status means, for refreshing the DRAM row indicated by the refresh counter when the memory full signal and the refresh due signal are simultaneously present.

2. The circuit according to claim 1 wherein the refresh control means refreshes a single row of data in the DRAM when the refresh due signal and the memory full signal are simultaneously present.

3. The circuit according to claim 1 wherein the memory status means comprises:

read indicating means for serially indicating a value corresponding to a recently read storage element in the FIFO memory;

write indicating means for serially indicating a value corresponding to a recently written storage element in the FIFO memory; and

logic means, coupled to read indicating means and to the write indicating means, for providing the memory full signal in response to the values indicated by the read indicating means and the write indicating means.

4. The circuit according to claim 3 wherein the said indicating means comprises a plurality of serially connected flip-flops forming a first shifter including a first flip-flop and a last flip-flop, an output terminal of the last flip-flop being coupled to an input terminal of the first flip-flop so that a binary sequence may be shifted in a continuous ring, and wherein only one active bit exists in the first shifter at any one time.

5. The circuit according to claim 4 wherein each flip-flop in the first shifter corresponds to a memory element in the FIFO memory, and wherein the active bit for the first shifter resides in the first shifter flip-flop corresponding to the most recently read memory element.

6. The circuit according to claim 4 wherein the write indicating means comprises a plurality of serially connected flip-flops forming a second shifter including a first flip-flop and a last flip-flop, an output terminal of the last flip-flop being coupled to an input terminal of the first flip-flop so that a binary sequence may be shifted in a continuous ring, and wherein only one active bit exists in the second shifter at any one time.

7. The circuit according to claim 6 wherein each flip-flop in the second shifter corresponds to a memory element in the FIFO memory, and wherein the active bit for the second shifter resides in the second shifter flip-flop corresponding to the most recently written memory element.

8. The circuit according to claim 3 wherein the FIFO memory comprises ten memory elements, and wherein the memory status means provides the memory full signal when eight, nine, or ten memory elements contain data.

9. A method for providing a continuous stream of data from a DRAM which is periodically refreshed by a refresh circuit comprising the steps of:

communicating data from the DRAM to the FIFO memory;

providing a memory full signal when the FIFO memory contains a selected amount of data from the DRAM;

providing a refresh due signal at fixed periodic time intervals;

sequentially providing DRAM row address values with a refresh counter; and

refreshing the DRAM row indicated by the refresh counter when the memory full signal and the refresh due signal are simultaneously present.

10. The method according to claim 9 wherein the refreshing step comprises the step of refreshing a single row of data in the DRAM when the refresh due signal and the memory full signal are simultaneously present.

11. The method according to claim 10 wherein the memory full signal providing step comprises:

serially indicating a first value corresponding to a recently read storage element in the FIFO memory;

serially indicating a second value corresponding to a recently written storage element in the FIFO memory; and

providing the memory full signal in response to the values indicated by the read indicating means and the write indicating means.

12. The method according to claim 11 wherein the first value indicating step comprises the step of shifting a plurality of binary signals containing only one read active bit through a plurality of read signal positions forming a continuous ring.

13. The method according to claim 12 wherein each read signal position corresponds to a memory element in the FIFO memory, and wherein the read active bit resides in the read signal position corresponding to the most recently read memory element.

14. The method according to claim 12 wherein the second value indicating step comprises the step of shifting a plurality of binary signals containing only one write active bit through a plurality of write signal positions forming a continuous ring.

15. The method according to claim 14 wherein each write signal position corresponds to a memory element in the FIFO memory, and wherein the write active bit resides in the write signal position corresponding to the most recently written memory element.

16. The method according to claim 11 wherein the FIFO memory comprises ten memory elements, and wherein the memory full signal providing step comprises the step of providing the memory full signal when eight, nine, or ten memory elements contain data.