Modular multistage switch for a parallel computing system

• US 5,123,011 A
• Filed: 09/27/1989
• Issued: 06/16/1992
• Est. Priority Date: 09/27/1989
• Status: Expired due to Fees

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: General Electric Company
• Inventors: Zieger, Richard M., Hein, Carl E.
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): HOM, SHICK C
• Application Number:
  US07/414,496
• Time in Patent Office: 993 Days
• Field of Search: 370/94.3, 370/60, 370/60.1, 370/58.1, 370/58.2, 370/58.3, 370/65, 370/65.5, 340/825.02, 340/825.8, 340/825.79, 340/826, 379/271, 379/272, 379/273, 178/3
• US Class Current: 370/380
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/1523 Parallel switch fabric planes
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04Q 3/521 using semiconductors in the switching stages

Abstract

A switched inerconnection system for interconnecting the data input and output ports of a plurality of individual data processors, terminals, sensors, robots or the like of a parallel data processing system includes a plurality of identical modules and custom interconnections. Each module includes on-board interconnections between input and output ports for providing interconnections among the processors coupled to that module, for thereby reducing the number of customized interconnections between modules.

Claims

1. A modular multistage switch for simultaneously communicating between a system output port and a system input port, where said system input and output ports each include at least first and second data paths, each module comprising:

a first stage of blocking switch means, said first stage of blocking switch means including an input port with M₁ data paths and an output port with N₁ data paths, where one of the M₁ data paths of said input port of said first stage of switch means are connected to one of the N₁ data paths of said output port of said first stage of switch means, said first stage of blocking switch means comprising;

a first substage of full crossbar switch means including an input port of P₁ data paths and an output port of Q₁ data paths, where P₁ =M1/2, Q₁ M1/2, and where one of the P₁ data paths of said input port of said first substage of switch means is connected to one of the Q₁ data paths of said output port of said first substage of switch means, said input port of said first substage of switch means constituting one portion of said input port of said first stage of blocking switch means;

a second substage of full crossbar switch means including an input port of P₂ data paths and an output port of Q₂ data paths, where P₂ =M1/2, Q₂ =M1/2, and where one of the P₂ data paths of said input port of said second substage of switch means is connected to one of the Q₂ data paths of said output port of said second substage of switch means, said input port of said second substage of switch means constituting an other portion of said input port of said first stage of blocking switch means;

a third substage of full crossbar switch means including an input port of P₃ data paths and an output port of Q₃ data paths, where P₃ 1/2, Q₃ =M1/2 and where one of the P₃ data paths of said input port of said third substage of switch means is connected to one of the Q₃ data paths of said output port of said third substage of switch means, said output port of said third substage of switch means constituting one portion of said output port of said first stage of blocking switch means;

a fourth substage of full crossbar switch means including an input port of P₄ data paths and an output port of Q₄ data paths, where P₄ =M1/2, Q₄ =M1/2 and where one of the P₄ data paths of said input port of said fourth substage of switch means is connected to one of the Q₄ data paths of said output port of said fourth substage of switch means, said output port of said fourth substage of switch means constituting an other portion of said output port of said first stage of blocking switch means;

sixth interconnection means coupled to a first portion of said output port of said first substage of switch means and to a first portion of said input port of said third substage of switch means;

seventh interconnection means coupled to a second portion of said output port of said first substage of switch means and to a first portion of said input port of said fourth substage of switch means;

eighth interconnection means coupled to a first portion of said output port of said second substage of switch means and to a second portion of and input port of said third substage of switch means; and

ninth interconnection means coupled to a second portion of said output port of said second substage of switch means and to a second portion of said input port of said fourth substage of switch means;

a second stage of blocking switch means, said second stage of switch means including an input port with M₂ data paths and an output port with N₂ data paths, where one of the M₂ data paths of said input port of said second stage of switch means is connected to one of the N₂ data paths of said output port of said second stage of switch means, said second stage of blocking switch means comprising;

a fifth substage of full crossbar switch means including an input port of P₅ data paths and an output port of Q₅ data paths, where P₅ =M2/2, Q₅ =M2/2, and where one of the P₅ data paths of said input port of said fifth substage of switch means is connected to one of the Q₅ data paths of said output port of said fifth substage of switch means, said input port of said fifth substage of switch means constituting one portion of said input port of said second stage of blocking switch means;

a sixth substage of full crossbar switch means including an input port of P₆ data paths and an output port of Q₆ data paths, where P₆ =M2/2, Q₆ =M2/2, and where one of the P₆ data paths of said input port of said sixth substage of switch means is connected to one of the Q₆ data paths of said output port of said sixth substage of switch means, said input port of said sixth substage of switch means constituting an other portion of said input port of said second stage of blocking switch means;

a seventh substage of full crossbar switch means including an input port of P₇ data paths and an output port of Q₇ data paths, where P₇ =M2/2, Q₇ =M1/2, and where one of the P₇ data paths of said input port of said seventh substage of switch means is connected to one of the Q₇ data paths of said output port of said seventh substage of switch means, said output port of said seventh substage of switch means constituting one portion of said output port of said second stage of blocking switch means;

an eighth substage of full crossbar switch means including an input port of P₈ data paths and an output port of Q₈ data paths, where P₈ =M2/2, Q₈ =M1/2, and where one of the P₈ data paths of said input port of said eights substage of switch means is connected to one of the Q₈ data paths of said output port of said eighth substage of switch means, said output port of said eighth substage of switch means constituting an other portion of said output port of said second stage of switch means;

tenth interconnection means coupled to a first portion of said output port of said fifth substage of switch means and to a first portion of said input port of said seventh substage of switch means;

eleventh interconnection means coupled to a second portion of said output port of said fifth substage of switch means and to a first portion of said input port of said eighth substage of switch means;

twelfth interconnection means coupled to a first portion of said output port of said sixth substage of switch means and to a second portion of said input port of said seventh substage of switch means;

thirteenth interconnection means coupled to a second portion of said output port of said sixth substage of switch means and to a second portion of said input port of said eights substage of switch means;

first interconnection means, coupled to said input port of said first stage of blocking switch means and adapted to be interconnected with said system output port;

second interconnection means, coupled to said output port of said second stage of blocking switch means and adapted to be interconnected with said system input port;

third interconnection means coupled to data paths of a portion of said output port of said first blocking switch means and adapted to be interconnected with switch means of other similar modules;

fourth interconnection means coupled to data paths of a portion of said input port of said second blocking switching means and adapted to be interconnected with switch means of other similar modules; and

fifth interconnection means coupled to data paths of a portion of said output port of said first blocking switch means and to data paths of a portion of said input port of said second blocking switch means for local communication between said system input and output ports.

2. A system according to claim 1, wherein:

said third interconnection means includes a first portion coupled to a first portion of said Q₃ data paths of said output ports of said third substage of switch means and a second portion coupled to a first portion of said Q₄ data paths of said output port of said fourth substage of switch means;

said fourth interconnection means includes a first portion coupled to a first portion of said P₅ data paths of said input port of said fifth substage of switch means and a second portion coupled to a first portion of said P₆ data paths of said input port sixth substage of switch means; and

said fifth interconnection means includes (1) a first intraconnection portion coupled to a second portion of said Q₃ data paths of said output port of said third substage of switch means and to a second portion of said P₆ data paths of said input port of said sixth substage of switch means, (2) a second intraconnection portion coupled to a third portion of said Q₃ data paths of said output port of said third substage of switch means and to a second portion of said P₅ data paths of said input port of said fifth substage of switch means, (3) a third intraconnection portion coupled to a second portion of said Q₄ data paths of said output port of said fourth substage of switch means and to a third portion of said P₆ data paths of said input port of said sixth substage of switch means, and (4) a fourth intraconnection portion coupled to a third portion of said Q₄ data paths of said fourth substage of switch means and to a third portion of said P₅ data paths of said input port of said fifth substage of switch means.

3. A system according to claim 2 wherein said P₁ data paths of said input port of said first substage of switch means and said Q₈ data paths of said output port of said eights substage of switch means, are combined to form bidirectional paths, and said P₂ data paths of said input port of said second substage of switch means and said Q₇ data paths of said output port of said seventh substage of switch means are combined to form bidirectional paths.