Arrangement and method for identifying and localizing faulty circuits of a memory module

• US 5,123,016 A
• Filed: 02/01/1990
• Issued: 06/16/1992
• Est. Priority Date: 08/26/1987
• Status: Expired due to Term

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Ritter, Hartmut, Muller, Bruno
• Primary Examiner(s): Beausoliel, Robert W.
• Application Number:
  US07/459,709
• Time in Patent Office: 866 Days
• Field of Search: 371/10.1, 371/10.2, 371/10.3, 371/11.1, 371/21.1, 371/21.2, 371/21.3, 371/21.6, 371/22.5, 371/15.1, 365/200, 365/201, 364/200, 364/900
• US Class Current: 714/711
• CPC Class Codes: G06F 11/2205 using arrangements specific to the hardware being tested
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

The identification of a faulty memory cells of a memory module ensues with the assistance of a selt-test method for whose implementation a processor (TPZ) is co-integrated on the memory module. In test mode, the test processor generates test patterns for the memory cells of the memory under test, evaluates the result signals output by the memory cells as a result of the test patterns and stores the addresses of memory cells that were identified as being faulty. With the assistance of the addresses of the faulty memory cells, the test processor produces a repair plan on the basis whereof rows and clumns having faulty memory cells are replaced with the assistance of replacemnet rows and replacement columns.

Claims

1. An arrangement for identifying and localizing faulty memory cells of a memory under test, comprising:

(a) a test processor integrated on a memory module together with the memory under test;

(b) replacement rows and/or replacement columns of memory cells in the memory under test employable for repair of the memory under test;

(c) the test processor including;

means for generating test patterns for the memory under test during a test mode,

means for evaluating resulting signals output by the memory under test in response to the test patterns to identify faulty memory cells, and

means for storing an addresses of faulty memory cells identified by said means for evaluating;

(d) the test processor including means for producing a repair plan for the faulty memory cells at the addresses stored by said means for storing, said repair plan designating rows and/or columns of the memory under test having the faulty memory cells to be replaced by the replacement rows and/or replacement columns;

(e) a drive circuit for the replacement rows and/or replacement columns of memory cells including EPROM cells; and

(f) means for programming said EPROM cells of said drive circuit so that the replacement rows and/or replacement columns replace the rows and/or columns having the faulty memory cells.

2. An arrangement according to claim 1, wherein the test processor further includes:

(a) an instruction memory in which test programs are stored;

(b) a data path having

(b1) an arithmetic logic unit that is connected to a data and address bus leading to the memory under test;

(b2) a register set connected to the data and address bus;

(b3) a constant memory in which constants are stored and that is connected to the data and address bus;

(c) and comprising a data path controller that generates control signals for said arithmetic logic unit, said register set and said constant memory of the data path dependent on instructions of the test programs supplied by the instruction memory.

3. An arrangement according to claim 2, wherein said data path controller includes,

(a) an instruction register that is composed of two sub-registers in which a respective instruction word can be stored;

(b) an address decoder that decodes the addresses contained in the instruction word for one of the register set and the constant memory;

(c) a program counter that is a counter, can be loaded in parallel and that generates the addresses of the instruction words; and

(d) an instruction decoder that generates control signals for said arithmetic unit, said register set and said constant memory of the data path from the instruction words.

4. An arrangement according to claim 3, further comprising:

an instruction decoder including

(a) an arithmetic logic unit decoder that generates control signals for the data path from an operation code of the instruction word;

(b) a branch decoder that loads a branch address in the instruction counter corresponding to the operation code of an instruction word and to the status of interrogation bits;

(c) a clock generator.

5. An arrangement according to claim 4, further comprising:

means for storing addresses of the memory cells in the register set.

6. An arrangement according to claim 4, further comprising:

means for storing test patterns in the constant memory.

7. An arrangement according to claim 1, wherein said test processor includes means for providing four instruction types, a first of said instruction types being for memory operations, a second of said instruction types being for arithmetic operations, a third of said instruction types being for Boolean operations, and a fourth of said instruction types being for branch operations.

8. An arrangement according to claim 1, wherein the test processor includes means for executing a self-test before testing the memory under test.

9. A method for identifying and localizing faulty memory cells of a memory to be tested, comprising the following steps:

(a) at the beginning of a test procedure, bringing the memory to be tested arranged on a memory module with a test processor into an initial condition by said test processor;

(b) in a test mode, generating test patterns for the memory to be tested using the test processor,

evaluating resulting signals output by the memory to be tested in response to the test patterns to identify faulty memory cells and

storing addresses of the faulty memory cells identified in said evaluating step;

(c) the test processor producing a repair plan for the faulty memory cells using the addresses stored during said storing step, rows/columns having faulty memory cells being replaceable by replacement rows/replacement columns according to said repair plan;

(d) the test processor determining whether a repair is still possible;

terminating the test given a negative result thereof and reporting the module as being irreparable given a negative result;

given a positive result, continuing steps (b) through (d) until the entire memory has been tested;

(e) after the conclusion of the test, the test processor determining whether faulty memory cells have been found;

when no faulty memory cells have been found during said test, reporting the module as being fault-free;

when, by contrast, faulty memory cells have been found during said test, programming EPROM cells arranged in a drive circuit for the replacement rows/replacement columns according to the repair plan, so that the replacement row/replacement column replaces the row/column having the faulty memory cells.

10. A method according to claim 9, wherein the processor for registering a faulty memory cell executes the following steps:

(a) checking as to whether the identified address of a faulty memory cell has already been stored and ending the test procedure in this case;

otherwise, continuing the test procedure with step (b);

(b) checking as to whether the number of faults per row is one higher than the number n of replacement columns and, in this case, ending the test procedure but, if the number of faults per row is not higher than the number n of replacement columns, continuing with step (c);

(c) checking as to whether the number of faults per column is one higher than the number m of replacement rows; and

, in this case, ending the test procedure but, if the number of faults per row is not higher than the number m of replacement rows, continuing with step (d);

(d) determining whether the number of faults exceeds the maximally allowable number per module and, in this case, reporting the module to be faulty, but otherwise storing the address of the faulty cell.

11. A method according to claim 10, further comprising the step of:

achieving the maximum number of faults when the number of faults reaches the maximum value R where R=m(n+1)+n(m+1), m=the number of replacement rows and n=the number of replacement columns.

12. A method according to claim 9, further comprising the steps of:

identifying a fault-free region of the memory at the beginning of a test procedure by the test processor and

storing the addresses of the faulty memory cells in this region.

13. A method according to claim 9, further comprising the step of:

repairing first rows or columns wherein the most faults occur.