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Arrangement and method for identifying and localizing faulty circuits of a memory module

  • US 5,123,016 A
  • Filed: 02/01/1990
  • Issued: 06/16/1992
  • Est. Priority Date: 08/26/1987
  • Status: Expired due to Term
First Claim
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1. An arrangement for identifying and localizing faulty memory cells of a memory under test, comprising:

  • (a) a test processor integrated on a memory module together with the memory under test;

    (b) replacement rows and/or replacement columns of memory cells in the memory under test employable for repair of the memory under test;

    (c) the test processor including;

    means for generating test patterns for the memory under test during a test mode,means for evaluating resulting signals output by the memory under test in response to the test patterns to identify faulty memory cells, andmeans for storing an addresses of faulty memory cells identified by said means for evaluating;

    (d) the test processor including means for producing a repair plan for the faulty memory cells at the addresses stored by said means for storing, said repair plan designating rows and/or columns of the memory under test having the faulty memory cells to be replaced by the replacement rows and/or replacement columns;

    (e) a drive circuit for the replacement rows and/or replacement columns of memory cells including EPROM cells; and

    (f) means for programming said EPROM cells of said drive circuit so that the replacement rows and/or replacement columns replace the rows and/or columns having the faulty memory cells.

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