Timing control method in a common bus system having delay and phase correcting circuits for transferring data in synchronization and time division slot among a plurality of transferring units

• US 5,123,100 A
• Filed: 01/10/1990
• Issued: 06/16/1992
• Est. Priority Date: 01/13/1989
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kondo, Takashi, Hisada, Isao
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Lim, Krisna
• Application Number:
  US07/462,816
• Time in Patent Office: 888 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 370/85.1, 340/825.2, 340/825.14
• US Class Current: 713/401
• CPC Class Codes: G06F 13/372 using a time-dependent priority, e.g. individually loaded time counters or time slot

Abstract

In a common bus control method, transmission and reception buses are connected to a unit having a unit number 1. A synchronization frame head signal for time-division slots of common buses is sequentially supplied to the units in the order of the unit numbers 1 to n through delay circuits. Phase correcting circuits are respectively connected to the transmission and reception buses of each unit so as to perform phase correction of data on the buses and latch signals for latching the data. The delay circuit arranged in each unit sets transmission delay data having an inherent delay difference on the basis of the synchronization frame head signal. An output from the delay circuit of each unit is used as the latch signal.

Claims

1. A timing control method in a common bus system in which n units having unit numbers 1 to n are connected through a common-time-division bus, said units being connected in series and in the order of the unit numbers, said common-time-division controlled bus comprising transmission and reception buses providing access to each of said units, said transmission and reception buses being connected together at said unit number 1, and a plurality of phase correcting means corresponding to said units, each of said phase correcting means performing a phase correction of data based on base clock signals generated in the unit number 1 when data are transmitted/received from one of said units to an adjacent unit, said method comprising the steps of:

setting a transmission delay information with a specific delay difference which is determined in accordance with the unit number of each of said units, said transmission delay being based on a synchronization frame head signal generated in the unit number 1; and

preparing a timing signal which determines a transmission time slot for the data transmission on the common-time-division controlled bus based on the received transmission delay information, said transmission time slot having a timing difference relative to the adjacent unit and being set between reception time slots;

said unit number 1 transmitting said first and second fundamental signals which are based on the synchronization frame head signal to said unit with the unit number 2;

each of said units having the units number 2 to n sequentially receiving first and second fundamental signals having a fixed delay difference which are prepared in the last unit to transmit delayed first and second fundamental signals being made respectively by adding additional fixed delay differences to the received first and second fundamental signals.

2. A timing control method in a common bus system according to claim 1, further comprising means in each of the units for preparing said timing signal, and means in each of said units number 2 to n controlled by said base clock signals for transmitting data to the next unit.

3. A timing control method in a common bus system according to claim 1 wherein each of said units having unit numbers 2 to n has means for detecting a transmission delay information which is to be set in the unit itself in accordance with said received transmission delay information.