Topography of CMOS microcomputer integrated circuit chip including core processor and memory, priority, and I/O interface circuitry coupled thereto
First Claim
1. A CMOS integrated circuit microcomputer including first, second, third, and fourth successive edges, the microcomputer comprising in combination:
- (a) a microprocessor including (i) address output buffer means located along a lower left edge and a bottom edge of the microprocessor, (ii) data bus buffer means located along a right edge of the microprocessor, and (iii) a plurality of interrupt circuits located along an upper edge of the microprocessor;
(b) a plurality of low order address buffer circuits located along a lower part of the first edge, adjacent to the address output buffer means of the microprocessor;
(c) a plurality of high order address buffer circuits located along a left part of the second edge, adjacent to the address buffer means of the microprocessor;
(d) chip selection output circuitry located along a right part of the second edge;
(e) a plurality of data bus buffer circuits located along a lower part of the third edge;
(f) a plurality of interrupt circuits located along an upper part of the third edge;
(g) a plurality of interrupt circuits located along a right part of the fourth edge;
(h) a first memory circuit located between the data bus buffer circuits and the microprocessor above the chip select output circuit means;
(i) a second memory circuit located directly above and adjacent to the microprocessor;
(j) a first group of interface circuits disposed between the fourth edge and the second memory circuit;
(k) a plurality of I/O interface circuits various ones of which are located along the fist, second, third, and fourth edges among the low order and high order address buffer circuits, the data bus buffer circuits, the interrupt circuits, and the first group of interface circuits, respectively, various ones of the I/O interface circuits being multiplexed with a plurality of external terminals of the low order and high order address buffer circuits, the data bus buffer circuits, the interrupt circuits, and the first group of interface circuits, respectively; and
(l) chip control circuit means located along an upper part of the first edge for operatively coupling the microprocessor to the first and second memory circuits, the first group of interface circuits, the chip selection output circuitry, the high and low order address buffer circuits, the data bus buffer circuits, and the I/O interface circuits.
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Abstract
The topography of a CMOS microcomputer chip includes first, second, third, and fourth consecutive edges, with chip control logic being located along the upper left edge. Five peripheral I/O port buffer circuits are located around the edge of the periphery of the chip, except for an eight bit peripheral output port located along the lower right edge and multiplexed with chip select outputs. The microcomputer includes an eight bit W65CO2S CMOS microprocessor, 192 bytes of SRAM, 4096 bytes of SROM, 22 edge interrupt inputs, 3 level-sensitive interrupt inputs, a UART, serial interface buffer for effectuating correction to a local area token passing network, four timers, and priority interrupt control circuitry. The topography is arranged to provide convenient connection of terminals of the microcomputer when it is used as a "core" of a larger computer system chip including an external memory system, a serial communication system, and an interrupt and I/O system. Static bus holding devices are connected to the memories on which I/O terminals are connected, and allow the microprocessor to interpret trinary logic states presented to the I/O port leads by external devices.
115 Citations
15 Claims
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1. A CMOS integrated circuit microcomputer including first, second, third, and fourth successive edges, the microcomputer comprising in combination:
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(a) a microprocessor including (i) address output buffer means located along a lower left edge and a bottom edge of the microprocessor, (ii) data bus buffer means located along a right edge of the microprocessor, and (iii) a plurality of interrupt circuits located along an upper edge of the microprocessor; (b) a plurality of low order address buffer circuits located along a lower part of the first edge, adjacent to the address output buffer means of the microprocessor; (c) a plurality of high order address buffer circuits located along a left part of the second edge, adjacent to the address buffer means of the microprocessor; (d) chip selection output circuitry located along a right part of the second edge; (e) a plurality of data bus buffer circuits located along a lower part of the third edge; (f) a plurality of interrupt circuits located along an upper part of the third edge; (g) a plurality of interrupt circuits located along a right part of the fourth edge; (h) a first memory circuit located between the data bus buffer circuits and the microprocessor above the chip select output circuit means; (i) a second memory circuit located directly above and adjacent to the microprocessor; (j) a first group of interface circuits disposed between the fourth edge and the second memory circuit; (k) a plurality of I/O interface circuits various ones of which are located along the fist, second, third, and fourth edges among the low order and high order address buffer circuits, the data bus buffer circuits, the interrupt circuits, and the first group of interface circuits, respectively, various ones of the I/O interface circuits being multiplexed with a plurality of external terminals of the low order and high order address buffer circuits, the data bus buffer circuits, the interrupt circuits, and the first group of interface circuits, respectively; and (l) chip control circuit means located along an upper part of the first edge for operatively coupling the microprocessor to the first and second memory circuits, the first group of interface circuits, the chip selection output circuitry, the high and low order address buffer circuits, the data bus buffer circuits, and the I/O interface circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A CMOS integrated circuit microcomputer system, comprising in combination:
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(1) a microcomputer including first, second, third, and fourth successive edges, the microcomputer including (a) a microprocessor, the microprocessor including (i) address output buffer means located along a lower left edge of the microprocessor and a bottom edge of the microprocessor, (ii) data bus buffer means located along a right edge of the microprocessor, and (iii) a plurality of interrupt circuits located along an upper edge of the microprocessor; (b) a plurality of low order address buffer circuits located along a lower part of the first edge of the microcomputer, adjacent to the address output buffer means of the microprocessor; (c) a plurality of high order address buffer circuits located along a left part of the second edge of the microcomputer, adjacent to the address buffer means of the microprocessor; (d) a plurality of data bus buffer circuits located along a lower part of the third edge of the microcomputer; (e) a plurality of interrupt circuits located along an upper part of the third edge of the microcomputer; (f) a plurality of interrupt circuits located along a right part of the fourth edge of the microcomputer; (g) a first group of interface circuits disposed between the fourth edge of the microcomputer and the microprocessor; (h) a plurality of I/O interface circuits various ones of which are located along the first, second, third, and fourth edges of the microcomputer among the low order and high order address buffer circuits, the data bus buffer circuits, the interrupt circuits, and the first group of interface circuits, respectively, various ones of the I/O interface circuits being multiplexed with a plurality of external terminals of the low order and high order address buffer circuits, the data bus buffer circuits, the interrupt circuits, and the first group of interface circuits, respectively; (i) chip control circuit means located along an upper part of the first edge of the microcomputer for operatively coupling the microprocessor to the first group of interface circuits, the chip selection output circuitry, the high and low order address buffer circuits, the data bus buffer circuits, and the I/O interface circuits; (2) an external memory system disposed along a lower portion of the first edge of the microcomputer, entirely along the second edge of the microcomputer, and along a lower portion of the third edge of the microcomputer; and (3) an interrupt and I/O system disposed along the upper portion of the third edge of the microcomputer and the right portion of the fourth edge of the microcomputer, and coupled to the I/O and interrupt terminals of the microcomputer. - View Dependent Claims (14, 15)
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Specification