Battery capacity computing apparatus

• US 5,124,627 A
• Filed: 02/04/1991
• Issued: 06/23/1992
• Est. Priority Date: 02/07/1990
• Status: Expired due to Fees

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Okada, Tetsuya
• Primary Examiner(s): Hickey, R. J.
• Application Number:
  US07/650,424
• Time in Patent Office: 505 Days
• Field of Search: 320/43, 320/44, 320/48, 320/636
• US Class Current: 320/136
• CPC Class Codes: G01R 19/16542 for batteries charge condition monitoring in G01R31/36
• CPC Class Codes: G01R 31/3648 comprising digital calculation means, e.g. for performing an algorithm
• CPC Class Codes: G01R 31/382 Arrangements for monitoring battery or accumulator variables, e.g. SoC

Abstract

A capacity computing apparatus for computing the capacity of a chargeable secondary battery by a microcomputer, wherein a resistance is connected to the secondary battery and a drop voltage because of charging and discharging current in the resistance is amplified by an amplifier, whereby the capacity of the secondary battery is computed on the basis of the amplified value. The capacity of the secondary battery is computed with good accuracy even with a small drop of the voltage in the resistance. Moreover, an influence of an offset voltage in the amplifier is removed by applying a constant voltage to the amplifier at all times. The stored value of the microcomputer is periodically updated, thereby avoiding an influence when the amplification degree of the amplifier is changed due to the temperature change.

Claims

1. A capacity computing apparatus for computing the capacity of a secondary battery, comprising:

a current-detecting resistor means connected in series with said secondary battery for detecting charging and discharging current of said secondary battery;

amplifying means for amplifying the output signal of said current-detecting resistor means, said amplifying means having a first amplifier which amplifies the output signal of said current-detecting resistor means when said secondary battery is charged, and a second amplifier which amplifies the output signal of said current-detecting resistor means when said secondary battery is discharged;

computing means for computing the capacity of said secondary battery on the basis of the output from said amplifying means;

a D/A converter which converts a digital signal as a reference generated from said computing means to an analog signal; and

comparing means for comparing the analog signal generated from said D/A converter with the output from said amplifying means, and outputting the comparative result to said computing means,

wherein said computing means computes the capacity of said secondary battery in response to the comparative result.

2. A capacity computing apparatus as set forth in claim 1, further comprising:

display means for displaying the computing result obtained by said computing means.

3. A capacity computing apparatus for computing the capacity of a secondary battery, comprising:

current-detecting means for detecting charging and discharging current of said secondary battery;

reference signal generating means for generating a reference signal to be superposed to the output signal of said current-detecting means;

amplifying means for superposing and amplifying the output signal of said current-detecting means and said reference signal; and

computing means for computing the capacity of said secondary battery on the basis of the output from said amplifying means.

4. A capacity computing apparatus as set forth in claim 3, wherein said computing means stores a reference computing result when the output signal of said current-detecting means is zero.

5. A capacity computing apparatus as set forth in claim 4, wherein said computing means computes the capacity of said secondary battery by substracting the reference computing result when the output signal of said current-detecting means is zero from the computing result when the output signal of said current-detecting means is not zero.

6. A capacity computing apparatus as set forth in claim 3, further comprising:

a first switch connected between an output terminal of said current-detecting means and an input terminal of said amplifying means; and

a second switch connected between the earth and the input terminal of said amplifying means.

7. A capacity computing apparatus as set forth in claim 6, wherein said first and second switches are periodically alternately changed over.

8. A capacity computing apparatus as set forth in claim 7, wherein the time while said first switch is closed is longer than the time while said second switch is closed.

9. A capacity computing apparatus as set forth in claim 8, wherein the period and time while said second switch is closed when said secondary battery is charged or discharged are shorter than those when said secondary battery is neither charged nor discharged.

10. A capacity computing apparatus as set forth in claim 3, wherein said current-detecting means is a resistance connected in series to said secondary battery.

11. A capacity computing apparatus as set forth in claim 3, wherein said amplifying means has a first amplifier which amplifies the output signal of said current-detecting means when said secondary battery is charged and, a second amplifier which amplifies the output signal of said current-detecting means when said secondary battery is discharged.

12. A capacity computing apparatus as set forth in claim 3, further comprising:

a D/A converter which converts a digital signal as a reference generated from said computing means to an analog signal; and

comparing means for comparing the analog signal generated from said D/A converter with the output from said amplifying means, and outputting the comparative result to said computing means,

wherein said computing means computes the capacity of said secondary battery in response to the comparative result.

13. A capacity computing apparatus as set forth in claim 12, further comprising:

display means for displaying the computing result obtained by said computing means.