Thin film transistor

• US 5,124,769 A
• Filed: 03/01/1991
• Issued: 06/23/1992
• Est. Priority Date: 03/02/1990
• Status: Expired due to Term

• Current Assignee: Nippon Telegraph and Telephone Corporation
• Original Assignee: Nippon Telegraph and Telephone Corporation
• Inventors: Suyama, Shiro, Tanaka, Keiji, Kato, Kinya, Nakazawa, Kenji
• Primary Examiner(s): Davie, James W.
• Application Number:
  US07/663,372
• Time in Patent Office: 480 Days
• Field of Search: 357/23.14, 357/23.7
• US Class Current: 257/66
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

The thin film transistor comprises source and drain regions, a channel forming region formed between the source and drain regions, a first (main) gate for turning on or off the transistor, and in particular at least one second (sub-) gate for reducing turn-off leakage current. When the n-channel transistor is turned off, for example, a negative voltage is applied to the main gate to form a p-channel layer in the channel forming region under the main gate and a positive voltage is applied to the subgate to form an n-channel layer in the channel forming region under the subgate, for instance, so that a pn junction can be formed between under the main gate and the subgate to reduce the turn-off leakage current. The above-mentioned disclosure can be clearly applied to p-channel transistors. Further, the above four-terminal transistor can be simply modified to a three-terminal transistor by connecting the main gate to the subgate via a diode or a capacitor or by directly connecting the drain region to the subgate. Further, the above three-terminal transistor can be manufactured in accordance with only the ordinary device manufacturing process.

Claims

1. A thin film transistor formed in a thin film semiconductor substrate, comprising:

(a) a source region formed of a first conductive type semiconductor film at a first end of the semiconductor substrate;

(b) a drain region formed of the same first conductive type semiconductor film at a second end of the semiconductor substrate;

(c) a channel forming region formed of the thin film semiconductor substrate having a low impurity concentration between said source and drain regions;

(d) a first gate formed over a first principal plane of said channel forming region via a first gate insulating film;

(e) a second gate formed over said channel forming region via a second gate insulating film;

(f) a first voltage supply for supplying voltage to said first gate; and

(g) a second voltage supply voltage to said second gate; and

wherein said first and second voltage supplies apply a first polarity voltage to said first and second gates to from first conductive type channel layers in said channel forming region under said first and second gate insulating film when the transistor is turned on, but said first voltage supply applies a second polarity voltage opposite to the first polarity to said first gate to form a second conductive type channel layer in said channel forming region only under said first gate insulating film and said second voltage supply applies the first polarity voltage to said second gate to maintain the first conductive type channel layer in said channel forming region under said second gate insulating film when the transistor is turned off, so that a pn junction can be formed in said channel forming region under between said first and second gate insulating films to reduce of current flowing between said source and drain regions.

2. The thin film transistor of claim 1, wherein said first gate and said second gate are formed on a first principal plane of said channel forming region.

3. The thin film transistor of claim 1, wherein said first gate is formed on a first principal plane of said channel forming region and said second gate is formed on a second principal plane opposite to the first principal plane of said channel forming region.

4. The thin film transistor of claim 1, which further comprises a third gate formed over said channel forming region via a third gate insulating film so as to sandwich the first gate between said second and third gates and wherein said first gate and said second and third gates are all formed on a first principal plane of said channel forming region.

5. The thin film transistor of claim 1, which further comprises a third gate formed over said channel forming region via a third gate insulating film so as to sandwich the first gate between said second and third gates and wherein said first gate is formed on a first principal plane of said channel forming region and said second and third gates are formed on a second principal plane opposite to the first principal plane of said channel forming region.

6. The thin film transistor of claim 1, wherein thickness of said second gate insulating film is smaller than that of said first gate insulating film.

7. The thin film transistor of claim 1, wherein dielectric constant of said second gate insulating film is larger than that of said first gate insulating film.

8. The thin film transistor of claim 1, wherein fixed charge of said second gate insulating film is larger than that of said first gate insulating film.

9. The thin film transistor of claim 2, wherein said second gate is connected to said first gate via a diode in the backward direction from said second gate to said first gate.

10. The thin film transistor of claim 2, wherein said second gate is connected to said first gate via a first diode in the backward direction from said second gate to said first gate and further connected to said drain region via a second diode in the backward direction from said second gate to said drain region.

11. The thin film transistor of claim 2, wherein said second gate is connected to said drain region via a conductive layer.

12. The thin film transistor of claim 2, wherein said second gate is connected to said first gate via a capacitor and further connected to said drain region via a diode in the backward direction from said second gate to said drain region.

13. The thin film transistor of claim 3, wherein said second gate is connected to said first gate via a diode in the backward direction from said second gate to said first gate.

14. The this film transistor of claim 3, wherein said second gate is connected to said first gate via a first diode in the backward direction from said second gate to said first gate and further connected to said drain region via a second diode in the backward direction from said second gate to said drain region.

15. The thin film transistor of claim 3, wherein said second gate is connected to said drain region via a conductive layer.

16. The thin film transistor of claim 3, wherein said second gate is connected to said first gate via a capacitor and further connected to said drain region via a diode in the backward direction from said second gate to said drain region.

17. The thin film transistor of claim 4, wherein said second and third gates are connected to said first gate via a diode in the backward direction from said second and third gates to said first gate.

18. The thin film transistor of claim 4, wherein said second and third gates are connected to said first gate via two diodes, respectively in the backward direction from said second and third gates to said first gate and further connected to said drain region via two different diodes in the backward direction from said second and third gates to said drain region.

19. The thin film transistor of claim 4, wherein said second and third gates are connected to said drain region via conductive layers.

20. The thin film transistor of claim 4, wherein said second and third gates are connected to said first gate via two capacitors, respectively and further connected to said drain region via two diodes, respectively in the backward direction from said second and third gates to said drain region.

21. The thin film transistor of claim 5, wherein and third gates are connected to said first gate via a diode in the backyard direction from said second and third gates to said first gate.

22. The thin film transistor of claim 5, wherein said second and third gates are connected to said first gate via two diodes, respectively in the backward direction from said second and third gates to said first gate and further connected to said drain region via two different diodes in the backward direction from said second and third gates to said drain region.

23. The thin film transistor of claim 5, wherein said and third gates are connected to said drain region via conductive layers.

24. The thin film transistor of claim 5, wherein said second and third gates are connected to said first gate via two capacitors, respectively and further connected to said drain region via two diodes, respectively in the backward direction from said second and third gates to said drain region.