Method for analyzing a signal by wavelets
First Claim
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1. A device for analysis by wavelets, comprising:
- an analog/digital converter enabling sampling and digitization of N points of an incoming signal S(t);
a clock circuit enabling delivery of a clock signal H0 at a sampling frequency to said converter, and clock signals Hl -Hp, corresponding sampling frequencies of which are submultiples of two of the sampling frequency of the clock signal H0 ;
a memory circuit enabling memorizing and delivery of wavelet Ψ
0 and scale Φ
0 signals; and
p sets of convoluters, a first set having two convoluters which receive and convolute said sampled and digitized incoming signal S(t) using said H1, Ψ
0 and Φ
0 signals and output a first pair of convoluted signals, and sets j for j≧
2 each including 2j convoluters receiving, two by two, respectively 2j-1 convoluted signals output by an order j-1 set, using the signals Ψ
0 and Φ
0 and a clock signal Hj ;
selection means for receiving all the convoluted signals from the convoluters and selecting at least one of the convoluted signals from the convoluters; and
means for interpreting the signals thus selected.
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Abstract
To analyze short-duration signals by means of an analysis using MARRAT'"'"'s algorithm with the wavelets of DAUBECHIES, at each step the correlation is done both on the signals coming from the correlation at the previous step by the scale ΦO signal and on the signals coming from the correlation at the preceding step by the signal ΦO. Thus, at the stage p, there is obtained a homogeneous signal consisting of 2p ×Np points of analysis. This makes it possible, in the method of analysis by wavelets, to obtain a depiction of the results having a homogeneous form making it easier to interpret them.
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Citations
6 Claims
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1. A device for analysis by wavelets, comprising:
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an analog/digital converter enabling sampling and digitization of N points of an incoming signal S(t); a clock circuit enabling delivery of a clock signal H0 at a sampling frequency to said converter, and clock signals Hl -Hp, corresponding sampling frequencies of which are submultiples of two of the sampling frequency of the clock signal H0 ; a memory circuit enabling memorizing and delivery of wavelet Ψ
0 and scale Φ
0 signals; andp sets of convoluters, a first set having two convoluters which receive and convolute said sampled and digitized incoming signal S(t) using said H1, Ψ
0 and Φ
0 signals and output a first pair of convoluted signals, and sets j for j≧
2 each including 2j convoluters receiving, two by two, respectively 2j-1 convoluted signals output by an order j-1 set, using the signals Ψ
0 and Φ
0 and a clock signal Hj ;selection means for receiving all the convoluted signals from the convoluters and selecting at least one of the convoluted signals from the convoluters; and means for interpreting the signals thus selected. - View Dependent Claims (2, 3)
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4. A device for analysis by wavelets of an input signal, comprising:
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a convoluter; a first memory circuit for storing and delivering signals Ψ
0 and Φ
0 to said convoluter;a clock circuit for delivering a clock signal H0 at a sampling frequency, and clock signals H1 -Hp having wherein the convoluter convolutes said input signal using said Ψ
0, Φ
0 and clock signals H0 -Hp, said intermediate computations of said convolution being stored by said second memory circuit, and produces a plurality of convoluted signals, at least one of said plurality of convoluted signals being selected by said selection circuit, thereby said convoluter performs all convolution computations of a multiple-stage convoluter. - View Dependent Claims (5, 6)
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Specification
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Current AssigneeThomson-CSF (Thales SA)
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Original AssigneeThomson-CSF (Thales SA)
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InventorsNicolas, Jean-Marie, Lemer, Alain
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Primary Examiner(s)Teska, Kevin J.
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Application NumberUS07/481,336Time in Patent Office854 DaysField of Search364/485, 364/486, 364/484, 364/421, 364/422, 364/728.01, 364/724.12, 364/728.03, 364/487US Class Current702/76CPC Class CodesG01R 23/16 Spectrum analysis; Fourier ...
