Method and apparatus for autoranging, quadrature signal generation, digital phase reference, and calibration in a high speed RF measurement receiver

• US 5,125,008 A
• Filed: 03/09/1990
• Issued: 06/23/1992
• Est. Priority Date: 03/09/1990
• Status: Expired due to Fees

• Current Assignee: Scientific-Atlanta Incorporated (Cisco Systems, Inc.)
• Original Assignee: Scientific-Atlanta Incorporated (Cisco Systems, Inc.)
• Inventors: Trawick, Charles D., Caldwell, Owen M.
• Primary Examiner(s): Chin, Stephen
• Application Number:
  US07/491,186
• Time in Patent Office: 837 Days
• Field of Search: 375/39, 375/98, 375/102, 375/7, 375/8, 375/10, 375/106, 455/234, 455/304, 329/320, 324/76, 324/77 R
• US Class Current: 375/349
• CPC Class Codes: G01S 7/4004 of parts of a radar system
• CPC Class Codes: G01S 7/4021 of receivers
• CPC Class Codes: G01S 7/4073 involving an IF signal injection

Abstract

Improved autoranging, calibration, and complex signal detection circuits for an intermediate frequency (IF) stage in a radio frequency (RF) measurement receiver. An improved autoranging circuit sets a gain stage of a selectively variable gain amplifier prior to each data acquisition cycle, to provide for wide dynamic range and rapid time domain response. An improved complex signal detection circuit for generating an inphase (I) and quadrature phase (Q) signal from an input IF signal in a signal channel and a reference channel is constructed with a novel commutating demodulator circuit. Calibration is effected with an improved digital phase reference method and apparatus wherein effectivr 90° phase shifts are digitially generated by shifting the generation sequence of timing signals for the complex signal detection circuit instead of phase shifting a known calibration signal, obviating the need for precision phase shifters, Doppler frequency generators, or Fourier transforms to obtain correction components for the optimum detection of complex signals.

Claims

1. An improved complex signal detection circuit responsive to an input signal having a predetermined frequency for converting said input signal into an inphase output signal and a quadrature phase output signal during a conversion cycle, comprising:

clock means for providing a clock signal having a frequency n times higher than said predetermined frequency of said input signal;

locking means for phase locking said clock signal and said input signal;

counter means for counting cycles of said clock signal modulo n and for providing count signals which subdivide a period of time corresponding to one cycle of said input signal;

memory means responsive to said count signals for providing inphase timing signals and quadrature phase timing signals, said quadrature phase timing signal being in quadrature with respect to said inphase timing signals during said conversion cycle;

a first switching circuit responsive to said inphase timing signals for providing I signal samples by switching between said input signal and an inverted input signal;

first integrating means for providing said inphase output signal by integrating said I signal samples for a predetermined number of periods of said input signal;

a second switching circuit responsive to said quadrature phase timing signals for providing Q signal samples by switching between said input signal and said inverted input signal; and

second integrating means for providing said quadrature phase output signal by integrating said Q signal samples for said predetermined number of periods of said input signal.

2. The improved complex signal detection circuit of claim 1, further comprising resetting means for resetting said first integrating means and said second integrating means at the conclusion of said conversion cycle.

3. The improved complex signal detection circuit of claim 1, further comprising synchronizing means for synchronizing said inphase timing signals and said quadrature phase timing signals to said clock signal and for providing synchronized inphase timing signals and synchronized quadrature phase timing signals.

4. The improved complex signal detection circuit of claim 3, wherein said synchronizing means comprises a latch circuit having said inphase timings signals and quadrature phase timing signals for inputs, said synchronized inphase timing signals and said synchronized quadrature phase timing signals as outputs, and operative to switch said inputs to said outputs in response to an edge of said clock signal.

5. The improved complex signal detection circuit of claim 1, wherein said memory means comprises a read only memory (ROM).

6. The improved complex signal detection circuit of claim 1, wherein n is at least 100.

7. The improved complex signal detection circuit of claim 1, wherein said first switching circuit and said second switching circuit comprise:

a unity gain inverter circuit for providing said inverted input signal;

a positive switching FET for switching said input signal to an input node for said integrating means, said input node corresponding to said I signal sample said Q signal sample for said second switching circuit;

a negative switching FET for switching said inverted input signal to said input node for said integrating means;

a positive shunt FET for switching said input signal to ground during operation of said negative switching FET;

a negative shunt FET for switching said inverted input signal to ground during operation of said positive switching FET;

and said FETs being switched on an off by said inphase timing signals for said quadrature phase timing signals for said second switching circuit.

8. The improved complex signal detection circuit of claim 1, wherein said first integrating means and said second integrating means comprise:

an operational amplifier having an integrating capacitor connected between an output terminal and an inverting input terminal, and

said I or said Q signal sample being connected to said inverting input terminal and ground being connected to said noninverting input terminal.

9. The improved complex signal detection circuit of claim 8, further comprising resetting means comprising at least one FET connected across the terminals of said integrating capacitor, said FET being operative in response to a resetting signal to discharge said integrating capacitor, and

wherein said memory means provides said resetting signal at the conclusion of said predetermined number of periods of said input signal.

10. The improved complex signal detection circuit of claim 1, further comprising calibration means for calibrating said inphase and said quadrature phase output signals, said calibration means comprising:

calibration signal means for providing a calibration signal having a known magnitude and a known phase relative to said clock signal;

phase offset signal storing means for storing a predetermined phase offset corresponding to a desired effective phase shift for said calibration signal;

said memory means being responsive to said count signals and to said predetermined phase offset stored in said phase offset signal storing means for generating phase-shifted inphase timing signals and phase-shifted quadrature phase timing signals,

whereby said inphase output signal and said quadrature phase output signals are generated with respect to said phase-shifted inphase timing signals and said phase-shifted quadrature phase timing signals so as to cause an effective shift in phase of said calibration signal without an actual phase shift in said calibration signal.

11. The improved complex signal detection circuit of claim 10, further comprising means for providing a plurality of said predetermined phase offsets during a calibration cycle so as to generate a set of inphase and quadrature phase values for a set of predetermined phase offsets, and

computing means responsive to said set of inphase and quadrature phase values for computing correction values to be utilized for correcting said inphase output signal and said quadrature output signal.

12. The improved complex signal detection circuit of claim 11, wherein said plurality of said predetermined phase offsets comprises 0°

, 90°

, 180°

, and 270°

.

13. The improved complex signal detection circuit of claim 1, further comprising phase walking means operative to cause said inphase output signal and said quadrature phase output signal to shift in phase by a predetermined incremental angular amount in response to a phase walk command.

14. The improved complex signal detection circuit of claim 13, wherein said phase walking means comprises a gate for inhibiting said counter means from counting for one cycle of said clock signal, thereby effectively shifting the generation of said inphase timing signals and said quadrature phase timing signals by an amount corresponding to one clock cycle, for each said conversion cycle.

15. An improved autoranging circuit for selecting one of a plurality of predetermined gain stages of amplification for an input signal, comprising:

analog to digital (A/D) converter means for providing a digital signal sample of said input signal;

timing means for timing a predetermined number of accumulation cycles;

memory means responsive to said digital signal sample of said input signal and an accumulated input signal value for providing as an output, for each one of said accumulation cycles, a sum of absolute values of said digital signal sample value and said accumulated input signal from a previous accumulation cycle;

storage means for storing said sum from said memory means as said accumulated input signal value for a next accumulation cycle;

programmed logic means responsive to said accumulated input signal value after said predetermined number of said accumulation cycles for providing gain selection signals; and

a selectively variable gain amplifier responsive to said gain selection signals for selecting one of said plurality of predetermined gain stages of amplification for said input signal, thereby providing a gain ranged output signal.

16. The improved autoranging circuit of claim 15, wherein said A/D converter is a flash converter.

17. The improved autoranging circuit of claim 15, wherein said memory means comprises a read only memory (ROM).

18. The improved autoranging circuit of claim 15, wherein said input signal is lower than a predetermined frequency, and wherein said predetermined number of accumulation cycles corresponds to an interval of time less than one period of said predetermined frequency.

19. The improved autoranging circuit of claim 18, wherein said predetermined frequency is about 100 kHz, and wherein said predetermined number of accumulation cycles is at least 50.

20. The improved autoranging circuit of claim 15, further comprising signal processing means for further processing said gain ranged output signal during a cycle of a frequency corresponding to the frequency of said input signal, and wherein autoranging circuit is operative to provide said gain ranged output signal prior to each cycle of said signal processing means.

21. The improved autoranging circuit of claim 20, wherein said signal processing means comprises complex signal means for providing an inphase and a quadrature phase signal corresponding to each cycle of said gain ranged output signal, and analog to digital converter means for digitizing said inphase and said quadrature phase signals, and

wherein said autoranging circuit is operative prior to each cycle of said signal processing means.

22. A method for calibrating a complex signal detection means, said complex signal detection means providing inphase and quadrature phase output signals in response to an input signal, comprising the steps of:

in response to a calibration command, generating a calibration reference signal;

providing said calibration reference signal as said input signal to said complex signal detection means;

generating timing signals for causing said complex signal detection means to convert said input signal into an inphase output signal and a quadrature phase output signal;

in response to said calibration command, providing a phase offset signal corresponding to a predetermined phase offset for said calibration reference signal;

in response to said phase offset signal, altering the timing of said timing signals for said complex signal detection means so that said complex signal detection means provides phase-offset inphase and quadrature phase output signals which are shifted in phase by an amount corresponding to said predetermined phase offset;

providing said phase-offset inphase and quadrature phase output signals to a computing device; and

calculating a calibration correction for gain and orthogonality for said complex signal detection means in response to said phase-offset inphase and quadrature phase output signals.

23. The method of claim 22, wherein the step of providing a phase offset signal comprises the steps of providing, in succession for a single calibration, a set of said phase offset signals, each one of said set of said phase offset signals corresponding to a different predetermined phase offset for said calibration reference signal.

24. The method of claim 22, wherein the method is performed in a radio frequency (RF) receiver.

25. The method of claim 24, wherein the RF receiver includes a local oscillator (LO) stage and an intermediate frequency (IF) stage, and wherein the complex signal detection means is associated with said IF stage.

26. The method of claim 25, wherein said LO stage provides said calibration reference signal.

27. The method of claim 26, wherein said calibration reference signal is phase-locked to a timing reference oscillator in said LO stage so as to provide a phase reference.

28. The method of claim 25, wherein the RF receiver is a measurement receiver including a measured signal channel and a reference signal channel, and wherein the method is performed for both said measured signal channel and said reference signal channel, and wherein said calibration reference signal is provided to both said measured signal channel and said reference signal channel.

29. The method of claim 22, wherein said complex signal detection means comprises an FET switched demodulator, and said timing signals for said complex signal detection means comprise signals for switching a plurality of FETs in said demodulator, and wherein the step of altering the timing of said timing signals comprises altering the timing of the signals for switching said FETs so that said complex signal detection means is operative as if there were a phase offset in said calibration reference signal.

30. The method of claim 29, wherein the steps of generating timing signals for said complex signal detection means and altering the timing of said timing signals comprises the steps of:

providing a precision timed clock signal;

providing a counter for counting occurrences of said clock signal;

providing a read only memory (ROM) responsive on some of its address lines to the states of said counter for generating said timing signals for said FETs from a first portion of memory;

providing said phase offset signal as other inputs for other address lines of said ROM;

in response to said phase offset signal, providing altered timing signals for said FETs from a second portion of memory in said ROM,

whereby said altered timing signals represent an effective shift in phase of said calibration reference signal when a phase offset signal is provided to said ROM.

31. An apparatus for calibration of a complex signal detection means, said complex signal detection means providing inphase and quadrature phase output signals in response to an input signal, comprising:

means responsive to a calibration command for generating a calibration reference signal;

means for providing said calibration reference signal as said input signal to said complex signal detection means;

timing signal means for generating timing signals for causing said complex signal detection means to convert said input signal into an inphase output signal and a quadrature phase output signal;

phase offset signal means responsive to said calibration command for providing a phase offset signal corresponding to a predetermined phase offset for said calibration reference signal;

timing signal altering means responsive to said phase offset signal for altering the timing of said timing signals for said complex signal detection means so that said complex signal detection means provides phase-offset inphase and quadrature phase output signals which are shifted in phase by an amount corresponding to said predetermined phase offset;

means for providing said phase-offset inphase and quadrature phase output signals to a computing device; and

means for calculating a calibration correction for gain and orthogonality for said complex signal detection means in response to said phase-offset inphase and quadrature phase output signals.

32. The calibration apparatus of claim 31, wherein said phase offset signal means comprises means for providing, in succession for a single calibration, a set of phase offset signals, each one of said set of said phase offset signals corresponding to a different predetermined phase offset for said calibration reference signal.

33. The calibration apparatus of claim 31, wherein said apparatus is utilized in a radio frequency (RF) receiver.

34. The calibration apparatus of claim 33, wherein said RF receiver includes a local oscillator (LO) stage and an intermediate frequency (IF) stage, and wherein said complex signal detection means is associated with said IF stage.

35. The calibration apparatus of claim 34, wherein said LO stage provides said calibration reference signal.

36. The calibration apparatus of claim 34, wherein said RF receiver is a measurement receiver including a measured signal channel and a reference signal channel, and wherein said calibration apparatus is utilized in both said measured signal channel and said reference signal channel, and wherein said calibration reference signal is provided to both said measured signal channel and said reference signal channel.

37. The calibration apparatus of claim 31, wherein said complex signal detection means comprises an FET switched demodulator, wherein said timing signals for said complex signal detection means comprise signals for switching a plurality of FETs in said demodulator, and wherein said timing signal altering means comprises means for altering the timing of signals for switching said FETs so that said complex signal detection means is operative as if there were a phase offset in said calibration reference signal.

38. The calibration apparatus of claim 31, wherein said timing signal means and said timing signal altering means comprises:

means for providing a precision timed clock signal;

means for counting occurrences of said clock signal;

a read only memory (ROM) responsive on some of its address lines to the states of said counting means for generating said timing signals from a first portion of memory;

means providing said phase offset signal as other inputs for other address lines of said ROM; and

said ROM being responsive to said phase offset signal for providing said altered timing signals from a second portion of memory in said ROM,

whereby said altered timing signals represent an effective shift in phase of said calibration reference signal when a phase offset signal is provided to said ROM.

39. The calibration apparatus of claim 38, wherein said complex signal detection means comprises an FET switched commutating demodulator, and wherein said timing signals and said altered timing signals comprise signals for switching a plurality of FETs an a sequence to generate said inphase and said quadrature phase output signals.

40. The calibration apparatus of claim 39, further comprising deskewing means connected to the outputs of said ROM for synchronizing said timing signals and said altered timing signals to said clock signal prior to connection for switching said FETs.

41. An apparatus for calibration of a complex signal detection means, said complex signal detection means providing inphase and quadrature phase output signals in response to an input signal, comprising:

means for providing a precision timed clock signal;

a counter for counting occurrences of said clock signal;

a read only memory (ROM) responsive on some of its address lines to the states of said counter for generating timing signals from a first portion of memory;

means responsive to a calibration command for generating a calibration reference signal;

means for providing said calibration reference signal as said input signal to said complex signal detection means;

phase offset signal means responsive to said calibration command for providing a phase offset signal as other inputs for other address lines of said ROM, said phase offset signal corresponding to a predetermined phase offset for said calibration reference signal;

said ROM being responsive to said phase offset signal for providing altered timing signals from a second portion of memory in said ROM;

means for synchronizing said timing signals and said altered timing signals from said ROM to said precision timed clock signal;

switching means responsive to timing signals synchronized by said synchronizing means for converting said input signal into inphase and quadrature phase output signals, said switching means being responsive to altered timing signals synchronized by said synchronizing means for converting said input signal into phase-offset inphase and quadrature phase output signals which are shifted in phase by an amount corresponding to said predetermined phase offset;

digital to analog (D/A) converter means for converting said inphase and quadrature phase output signals and said phase-offset inphase and quadrature phase output signals into digital inphase and quadrature phase output signals and digital phase-offset inphase and quadrature phase output signals;

means for providing said digital inphase and quadrature phase output signals and said digital phase-offset inphase and quadrature phase output signals to a computing means; and

means responsive to said digital inphase and quadrature phase output signals and said digital phase-offset inphase and quadrature phase output signals for computing a calibration correction for gain and orthogonality for signals provided by said switching means in response to said digital inphase and quadrature phase output signals and said digital phase-offset inphase and quadrature phase output signals,

whereby said altered timing signals represent an effective shift in phase of said calibration reference signal when a phase offset signal is provided to said ROM.

42. The calibration apparatus of claim 41, wherein said apparatus is utilized in an RF receiver including a local oscillator (LO) stage, and wherein said calibration reference signal is phase locked to a timing reference oscillator associated with said LO stage so as to provide a phase reference.

43. A signal processing circuit responsive to an input signal having a predetermined frequency and a wide dynamic range for providing an inphase output signal and a quadrature phase output signal corresponding to said input signal, comprising:

autoranging means for selecting one of a plurality of predetermined gain stages of amplification for said input signal and for providing a gain ranged output signal;

a complex signal detection circuit for converting said gain ranged input signal into an inphase output signal and a quadrature phase output signal during a conversion cycle; and

calibration signal means responsive to a calibration input signal provided during a calibration cycle for providing calibration correction signals to a utilization apparatus which utilizes said calibration correction signals to correct said inphase output signal and said quadrature phase output signal.

44. The circuit of claim 43, further comprising control means for controlling the operation of said autoranging means to provide said gain ranged output signal prior to each conversion cycle of said complex signal detection circuit.

45. The circuit of claim 43, wherein said autoranging means comprises:

input buffer means for receiving and buffering said input signal;

analog to digital (A/D) converter means for providing a digital signal sample of said input signal;

timing means for timing a predetermined number of accumulation cycles;

memory means responsive to said digital signal sample of said input signal and an accumulated input signal value for providing as an output, for each one of said accumulation cycles, a sum of the absolute value of said digital signal sample and said accumulated input signal value from a previous accumulation cycle;

storage means for storing said sum from said memory means as said accumulated input signal value for a next accumulation cycle;

programmed logic means responsive to said accumulated input signal value after said predetermined number of said accumulation cycles for providing gain selection signals; and

a selectively variable gain amplifier responsive to said gain selection signals for selecting one of said plurality of predetermined gain stages of amplification for said input signal, thereby providing said gain ranged input signal.

46. The circuit of claim 43, wherein said complex signal detection circuit comprises:

clock means for providing a clock signal having a frequency n times higher than said predetermined frequency of said input signal;

locking means for phase locking said clock signal and said input signal;

counter means for counting cycles of said clock signal modulo n and for providing count signals which subdivide a period of time corresponding to one cycle of said input signal;

memory means responsive to said count signals for providing inphase timing signals and quadrature phase timing signals, said quadrature phase timing signals being in quadrature with respect to said inphase timing signals during said conversion cycle;

a first switching circuit responsive to said inphase timing signals for providing I signal samples by switching between said input signal and an inverted input signal;

first integrating means for providing said inphase output signal by integrating said I signal samples for a predetermined number of periods of said input signal;

a second switching circuit responsive to said quadrature phase timing signals for providing Q signal samples by switching between said input signal and said inverted input signal; and

second integrating means for providing said quadrature phase output signal by integrating said Q signal samples for said predetermined number of periods of said input signal.

47. The circuit of claim 43, wherein said calibration signal means comprises:

means for providing a precision timed clock signal;

a counter for counting occurrences of said clock signal;

a read only memory (ROM) responsive on some of its address lines to the states of said counter for generating timing signals from a first portion of memory;

means responsive to a calibration command for generating a constant phase calibration reference signal;

means for providing said calibration reference signal as said input signal to said complex signal detection means;

phase offset signal means responsive to said calibration command for providing a phase offset signal as other inputs for other address lines of said ROM, said phase offset signal corresponding to a predetermined phase offset for said calibration reference signal;

said ROM being responsive to said phase offset signal for providing altered timing signals from a second portion of memory in said ROM;

means for synchronizing said timing signals and said altered timing signals from said ROM to said precision timed clock signal;

switching means responsive to timing signals synchronized by said synchronizing means for converting said input signal into inphase and quadrature phase output signals, said switching means being responsive to altered timing signals synchronized by said synchronizing means for converting said input signal into phase-offset inphase and quadrature phase output signals which are shifted in phase by an amount corresponding to said predetermined phase offset;

digital to analog (D/A) converter means for converting said inphase and quadrature phase output signals and said phase-offset inphase and quadrature phase output signals into digital inphase and quadrature phase output signals and digital phase-offset inphase and quadrature phase output signals;

means for providing said digital inphase and quadrature phase output signals and said digital phase-offset inphase and quadrature phase output signals to said utilization means; and

means associated with said utilization means responsive to said digital inphase and quadrature phase output signals and said digital phase-offset inphase and quadrature phase output signals for computing a calibration correction for gain and orthogonality for signals provided by said switching means in response to said digital inphase and quadrature phase output signals and said digital phase-offset inphase and quadrature phase output signals,

whereby said altered timing signals represent an effective shift in phase of said calibration reference signal when a phase offset signal is provided to said ROM.

48. A commutating demodulator circuit responsive to an input signal at a predetermined frequency for providing an output signal referenced to the phase of a known phase reference signal during a conversion cycle, comprising:

clock means for providing a clock signal having a frequency n times higher than said predetermined frequency of said input signal;

locking means for phase locking said input signal and said clock signal;

counter means for counting cycles of said clock signal modulo n and for providing count signals which subdivide a period of time corresponding to one cycle of said input signal;

memory means responsive to said count signals for providing timing signals during said conversion cycle, said timing signals comprising a positive switching signal, a negative switching signal, a positive shunt signal, and a negative shunt signal,

said positive switching signal and said negative switching signal being 180°

out of phase with respect to each other, and said positive shunt signal and said negative shunt signal being 180°

out of phase with respect to each other;

first switching means responsive to said positive switching signal for switching said input signal to an integrating node;

second switching means responsive to said negative switching signal for switching an inverted input signal to said integrating node;

third switching means responsive to said positive shunt signal for holding the input voltage of said first switching means near ground during said negative switching signal;

fourth switching means responsive to said negative shunt signal for holding the input voltage of said second switching means near ground during said positive switching signal; and

synchronizing means for synchronizing said timing signals to said clock signal.

49. The commutating demodulator circuit of claim 48, wherein said synchronizing means comprises a latch circuit having said timing signals from said memory means as inputs, having said positive switching signal, said negative switching signal, said positive shunt signal, and said negative shunt signal as outputs, and operative to switch said inputs to said outputs in response to an edge of said clock signal.

50. The commutating demodulator circuit of claim 49, wherein said first switching means, said second switching means, said third switching means, and said fourth switching means comprise FETs, and wherein said outputs of said latch circuit directly drive the gate terminals of said FETs.

51. The commutating demodulator circuit of claim 48, wherein said circuit comprises a complex signal detection circuit responsive to an input signal having a predetermined frequency for converting said input signal into an inphase output signal and a quadrature phase output signal during said conversion cycle.