Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller

• US 5,125,084 A
• Filed: 05/26/1988
• Issued: 06/23/1992
• Est. Priority Date: 05/26/1988
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bland, Patrick M., Begun, Ralph M., Dean, Mark E.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Von Buhr, Maria N.
• Application Number:
  US07/198,894
• Time in Patent Office: 1,489 Days
• Field of Search: 364/200, 364/900
• US Class Current: 712/33
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 9/3802 Instruction prefetching

Abstract

Any incompatibility between pipelined operations (such as is available in the 80386) and dynamic bus sizing (allowing the processor to operate with devices of 8-, 16- and 32-bit sizes) is accommodated by use of an address decoder and ensuring that device addresses for cacheable devices are in a first predetermined range and any device addresses for non-cacheable devices are not in that predetermined range. Since by definition cacheable devices are 32-bit devices, pipelined operation is allowed only if the address decoder indicates the access is to a cacheable device. In that event, a next address signal is provided to the 80386. This allows the 80386 to proceed to a following cycle prior to completion of the previous cycle. For accesses which are to devices whose address indicate they are non-cacheable, a next address signal is withheld until the cycle is completed, i.e. without pipelining. The invention further provides for proper interface between a DMA mechanism (driven by a first clock) and a CPU local bus subsystem (driven by an entirely different clock). Data provided by the DMA mechanism is latched into an interface between the CPU local bus and the system bus, and a DMA cycle completed. Only after completion of the DMA cycle is detected, is the cycle on the CPU local bus allowed to complete. In this fashion, the CPU can go on to a following operation and be assured that the DMA mechanism is no longer driving the system bus.

Claims

1. A microcomputer system comprising:

a processor of a given bit width for executing instructions,

first means including the processor for generating an address of a next instruction and initiating fetching of said next instruction during the execution of at least some currently executing instructions, whereby instructions may be prefetched for pipelined instruction execution,

additional means including the processor for generating a next instruction address and initiating fetching of a next instruction upon completing execution of a currently executing instruction for non-pipelined instruction execution,

a cache memory subsystem of said given bit width, having an address range for cacheable data, and coupled to said processor by a local bus,

a further bus connecting said local bus with addressable other components having said given bit width and with at least one addressable component of a reduced bit width for transferring data between said components and said processor and subsystem via said further bus and local bus during execution of certain of said instructions, at least some of said components having said given bit width having an address in said address range of said cache subsystem and at least one component of reduced bit width having an address outside said address range;

said processor further including means responsive to the execution of each of said certain instructions for asserting on said local bus a component address alternatively within or outside of said address range,

address decoder means responsive to each said asserted address on said local bus during the execution of said certain instructions for generating a signal indicating whether said asserted address is alternatively within or outside of said address range, and

logic means responsive to the signal generated by said address decoder for rendering said first means effective to generate a next instruction address for pipelined operation when said address decoder means indicates an asserted address within said address range and for rendering said additional means effective to generate a next instruction address for non-pipelined operation when said address decoder means indicates an asserted address outside said address range.

2. A system as recited in claim 1 further comprising:

a first interface coupled between said local bus and said further bus, and wherein said further bus comprises;

a system bus directly connected to said interface, at least some of said other components connected to said system bus;

a second interface directly connected between said system bus and an optional feature bus, where at least some of said other components are coupled to said optional feature bus for transferring data between said last mentioned components and said processor and subsystem via said first and second interfaces, said system bus and said optional feature bus.

3. A system as recited in claim 2 wherein said one component of a reduced bit width is directly connected to said optional feature bus for transferring data with said processor and subsystem via said first and second interface, said system bus and said optional feature bus.

4. A system as recited in claim 1 further comprising:

DMA control means coupled directly to said further bus and including

means effective during the execution of said certain instructions by the processor to initiate DMA cycles for controlling communication and data transfer between the processor and said other components via said local bus and said further bus, and

means effective at the end of each DMA cycle for notifying the additional means that the execution of a currently executing instruction is completed whereby the processor can initiate fetching of a next instruction.

5. A microprocessor system comprising:

a CPU, a cache subsystem having an address range for cacheable data and a local bus interconnecting said CPU and subsystem,

a system bus connected to the local bus by a buffer means for coupling functional units to said CPU and cache subsystem,

said CPU, cache subsystem, local bus, system bus and certain of said functional units having equal bit widths and others of said functional units having a smaller bit width,

at least some of said certain functional units, but none of said other functional units, having addresses within the address range of the cache subsystem,

said CPU including means for initiating a next cycle of operation,

an address decoder responsive to functional unit addresses generated by the CPU on the local bus during cycles of operation to determine whether or not they fall within the address range of the cache subsystem, and

logic means responsive to the address decoder for controlling operation of the CPU means by allowing it to proceed to a next cycle of operation prior to completion of a current cycle of operation when the decoded address is within said address range or alternatively stopping it from proceeding to the next cycle of operation until completion of the current cycle of operation when the decoded address is outside said address range.

6. A microprocessor system comprising:

a CPU, a cache subsystem having an address range for cacheable data and a local bus interconnecting said CPU and subsystem, said CPU, cache subsystem and local bus having equal bit widths,

a system bus coupled to the local bus by a buffer and an optional feature bus coupled to the system bus by an interface for coupling respective functional units to the CPU and cache subsystem,

said system bus, optional feature bus and certain of said functional units having a bit width equal to that of said CPU, cache subsystem and local bus and others of said functional units having a smaller bit width;

at least some of said certain functional units, but none of said other functional units, having addresses within the address range of the cache subsystem,

said CPU including means for initiating a next cycle of operation,

an address decoder responsive to functional unit addresses generated by the CPU on the local bus during each cycle of operation to determine whether or not they fall within the address range of the cache subsystem, and

logic means responsive to the address decoder for controlling operation of the CPU means by allowing it to proceed to a next cycle of operation prior to completion of a current cycle of operation when the decoded address is within said address range or alliteratively stopping it from proceeding to the next cycle of operation until completion of the current cycle of operation when the decoded address is outside said address range.

7. A microprocessor system comprising:

a CPU, a cache subsystem and a local bus interconnecting the CUP and cache subsystem, said CPU, cache subsystem and local bus having equal data bus widths,

said CPU including means for executing data transfer instructions directed to functional units and for generating a functional unit address on the local bus during the execution of each of said instructions;

a system bus coupled to said local bus for routing data transfers to and from the CPU during execution of said data transfer instructions;

said cache subsystem having a range of addresses including addresses assignable to functional unit having said equal data bus width;

addresses outside of said range of addresses including addresses assignable to other functional units of said equal data bus width and of smaller data bus widths;

said CPU including means for initiating a next instruction cycle;

an address decoder responsive to a functional unit address generated by the CPU on the local bus during the execution of each of said data transfer instructions to determine whether or not it falls within the address range of the cache subsystem; and

logic means responsive to the address decoder for controlling operation of the CPU means by allowing it to proceed to a next instruction cycle prior to completion of a current instruction cycle when the decoded address is within said address range or alliteratively stopping it from proceeding to the next instruction cycle until completion of the current instruction cycle when the decoded address is outside said address range.

8. A microcomputer system comprising:

a processor of a given bit width for executing instructions including data transfer instructions directed to functional units,

first means including the processor for generating an address of a next instruction and initiating fetching of said next instruction during the execution of at least some currently executing instructions, whereby instructions may be prefeteched for pipelined instruction execution,

additional means including the processor for generating a next instruction address and initiating fetching of a next instruction upon completing execution of a currently executing instruction for non-pipelined instruction execution,

a cache memory subsystem of said given bit width, having an address range for cacheable data, and coupled to said processor by a local bus,

a system bus for routing data transfers to and from the processor via said system bus and local bus during execution of said data transfer instructions,

addressees within said address range including addresses assignable to functional units having said given bit width,

addresses outside of said address range including addresses assignable to other functional units having said given bit width and to functional units having a smaller bit width than said given bit width,

said processor further including means responsive to the execution of each of said data transfer instructions for asserting on said local bus a functional unit address alternatively within or outside of said address range,

address decoder means responsive to each said asserted address on said local bus during the execution of said data transfer instructions for generating a signal indicating whether said asserted address is alternatively within or outside of said address range, and

logic means responsive to the signal generated by said address decoder for rendering said first means effective to generate a next instruction address for pipelined operation when said address decoder means indicates an asserted address within said address range and for rendering said additional means effective to generate a next instruction address for non-pipelined operation when said address decoder means indicates an asserted address outside said address range.

9. A microprocessor system comprising:

a CPU for executing certain instructions including data transfers directed to functional units and for generating functional unit address information on a local bus during the execution of said instructions;

a cache subsystem and a local bus interconnecting said CUP and subsystem;

a system bus and a buffer coupling the system bus to the local bus for routing said data transfers between the CPU and said functional units, said CPU, local bus and system bus having equal bit widths;

an address decoder responsive to said address information placed on the local bus by the CPU to determine whether or not the address falls within an address range of the cache subsystem;

logic means responsive to the address decoder during each data transfer for controlling operation of the CPU by allowing it to proceed to a next CPU instruction prior to completion of the data transfer when the decoded address is within said address range, and alliteratively stopping the CPU from proceeding to the next CPU instruction until completion of the data transfer when the decoded address is outside said address range;

addresses within said address range including addresses assignable to functional units having said equal data bus width; and

addresses outside said address range including addresses assignable to other functional units having said equal data bus width and functional units having a data bus width smaller than said equal data bus width.