Interrupt control for multiprocessor computer system

• US 5,125,093 A
• Filed: 08/14/1990
• Issued: 06/23/1992
• Est. Priority Date: 08/14/1990
• Status: Expired due to Fees

• Current Assignee: Nexgen Incorporated (Advanced Micro Devices, Inc.)
• Original Assignee: Nexgen Microsystems
• Inventors: McFarland, Harold L.
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US07/567,399
• Time in Patent Office: 679 Days
• Field of Search: 364/200, 364/230.2, 364/230.4, 364/230.6, 364/900, 364/941, 364/942.4
• US Class Current: 710/266
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

A technique that efficiently allocates the servicing of interrupts among a plurality of CPUs in a multiprocessor computer system requires no change in software that was written for a system with one CPU and one PIC. Symmetric and asymmetric configurations contemplate a primary CPU (15a) and one or more secondary CPU'"'"'s (15b-d) responding to and servicing multiple sets of interrupts. Both configurations include interrupt supervisory logic to support such operation. The symmetric configuration provides a PIC (20a-d) for each CPU in the system. All the PICs are located at the same I/O address, and separate provision is made to specify which PIC is to respond to an interrupt acknowledge cycle initiated by a particular CPU. The asymmetric configuration of the present invention provides PIC (20a) for the primary CPU (15a) only. That PIC'"'"'s interrupt line is communicated only to the primary CPU. Another mechanism, such as an ATTN facility (95), is provided to drive the secondary CPU'"'"'s interrupt inputs. Since the secondary CPUs lack PICs there is provided logic (48) that responds to an interrupt acknowledge operation from any of the secondary CPUs by driving a fixed, interrupt vector onto the data bus.

Claims

1. A multiprocessing computer system comprising:

a data bus;

an address bus;

a primary processor and at least one secondary processor coupled to said data bus and said address bus, each processor having an interrupt input;

a set of interrupt request (IRQ) lines;

a plurality of devices, each coupled to at least one of said IRQ lines and capable of asserting an interrupt request on at least one IRQ line to which it is coupled;

a programmable interrupt controller (PIC), coupled to at least one of said IRQ lines and to at least a portion of said data bus, said PIC being responsive to at least some interrupt requests received from at least one of said devices, and having means for communicating a given received interrupt request to the interrupt input of said primary processor;

MPIC means, including said PIC, and further including means coupled to at least one of said IRQ lines and to at least a portion of said data bus, being responsive to at least some interrupt requests received from at least one of said devices, for communicating a given received interrupt request to the interrupt input of a selected secondary processor;

means, included with each given processor, for carrying out an interrupt acknowledge operation in response to a received interrupt request, including (a) means for placing on said address bus an address that is specific to interrupt acknowledge operations but independent of any particular processor, and (b) means for communicating to said MPIC means an identifier that is specific to that given processor; and

means, included with said MPIC means and responsive to said identifier, (a) for causing said PIC to provide an interrupt vector on said data bus if said identifier specifies said primary processor, and (b) for providing an interrupt vector on said data bus if said identifier specifies a secondary processor.

2. The computer system of claim 1, and further comprising:

an attention flag defined to correspond to a particular one of said processors;

means for setting said attention flag in response to a set of conditions that requires that said address bus have placed thereon at least one particular address defined to correspond to the particular one of said processors; and

means for communicating the fact of setting of said attention flag to said MPIC means.

3. The computer system of claim 2 wherein said set of conditions also requires that said particular address be placed on said address bus in connection with a read operation.

4. The computer system of claim 3, and further comprising means for clearing said attention flag in response to a set of conditions that requires that said address bus have placed thereon at least one particular address defined to correspond to the particular one of said processors in connection with a write operation.

5. The computer system of claim 1 wherein said MPIC comprises a number of secondary PICs equal to the number of secondary processors to define at least a portion of said means for providing an interrupt vector on said data bus if said identifier specifies a secondary processor.

6. The computer system of claim 1, further comprising a set of Master ID (MID) lines coupled to said processors, and wherein said means for communicating to said MPIC means an identifier that is specific to that given processor comprises means for placing said identifier on said MID lines in connection with an interrupt acknowledge operation.

7. The computer system of claim 1 wherein said PIC has a plurality of interrupt request inputs, and wherein said MPIC means includes means, responsive to a configuration flag capable of assuming either of two states, for directing at least one type of interrupt request to one or the other of two specific interrupt request inputs, depending on the state of said configuration flag.

8. The computer system of claim 1 wherein said means for providing an interrupt vector on said data bus if said identifier specifies a secondary processor provides the same vector in response to at least two types of interrupt.

9. The computer system of claim 1 wherein said address and data buses comprise a set of time-multiplexed lines.

10. A multiprocessing computer system comprising:

a data bus;

an address bus;

a set of interrupt (IRQ) lines;

a plurality of processors coupled to said data bus and said address bus, each processor having an interrupt input;

at least one device coupled to at least one of said IRQ lines and capable of asserting an interrupt request on one of said interrupt request lines;

a plurality of programmable interrupt controllers (PICs), equal in number to the number of processors in said plurality of processors, each given PIC being defined to correspond to a respective one of said processors and having (a) a set of interrupt inputs coupled to at least one of said interrupt request lines, (b) an interrupt output coupled to the interrupt input of the respective one of said processors to which the given PIC is defined to correspond, and (c) a data port coupled to at least a portion of said data bus;

means included with each given processor, for carrying out an interrupt acknowledge operation with the PIC that is defined to correspond to that given processor, including means for placing on said address bus a PIC address that is specific to PICs but independent of any particular PIC, and means for generating an identifier that is specific to that given processor;

logic means, coupled to said means for carrying out an interrupt acknowledge operation and responsive to the occurrence of an interrupt acknowledge operation and to said identifier, (a) for selecting which PIC is to participate in the interrupt acknowledge operation, and (b) for applying control signals to the PIC so selected; and

means included with each given PIC, responsive to control signals from said logic means, for providing an interrupt vector on said data bus.

11. The computer system of claim 10, further comprising:

an attention flag defined to correspond to a particular one of said processors;

means for setting said attention flag in response to a set of conditions that requires that said address bus have placed thereon at least one particular address defined to correspond to the particular one of said processors; and

means for communicating the fact of setting of said flag to said logic means.

12. The computer system of claim 11 wherein said set of conditions also requires that said particular address be placed on said address bus in connection with a read operation.

13. The computer system of claim 12, and further comprising means for clearing said attention flag in response to a set of conditions that requires that said address bus have placed thereon at least one particular address defined to correspond to the particular one of said processors in connection with a write operation.

14. The computer system of claim 10 wherein each PIC has a plurality of interrupt request inputs, and wherein said logic means includes means, responsive to a configuration flag capable of assuming either of two states, for directing at least one type of interrupt request to one or the other of two specific interrupt request inputs, depending on the state of said configuration flag.

15. The computer system of claim 10 wherein said address and data buses comprise a set of time-multiplexed lines.

16. The computer system of claim 10, further comprising a set of Master ID (MID) lines coupled to said processors, and wherein:

said means for generating any identifier that is specific to that given processor operates to place said identifier on said MID lines; and

said logic means is coupled to said MID lines.