Process for the selective encapsulation of an electrically conductive structure in a semiconductor device

• US 5,126,283 A
• Filed: 05/21/1990
• Issued: 06/30/1992
• Est. Priority Date: 05/21/1990
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Filipiak, Stanley M., Pintchovski, Faivel, Yeargain, John R.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): HOLTZMAN, LAURA
• Application Number:
  US07/526,071
• Time in Patent Office: 771 Days
• Field of Search: 437/192, 437/194, 437/246, 437/983, 437/188, 437/197, 148/DIG. 18
• US Class Current: 438/396
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02244 of a metallic layer
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/31683 of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/911 Differential oxidation and etching

Abstract

A process for fabricating an improved semiconductor device is disclosed wherein a protective layer of Al₂ O₃ is selectively formed to encapsulate a refractory-metal conductor. To form the Al₂ O₃ layer, first an Al/refractory-metal alloy is selectively formed on the surface of the refractory-metal conductor, then the Al/refractory-metal alloy is reacted with O₂. The resulting Al₂ O₃ encapsulation layer acts as an O₂ diffusion barrier preventing the oxidation of the refractory-metal during subsequent process steps used to fabricate the semiconductor device. In addition, the Al₂ O₃ layer improves the mechanical compatibility of the refractory-metal conductor with other materials used to construct the semiconductor device, such as, for example, improving the adhesion of an overlying layer of passivation glass to the refractory-metal conductor.

Claims

1. A method for fabricating a semiconductor device comprising:

providing a substrate having a device region thereon;

forming a dielectric layer to overlie the substrate;

forming a refractory-metal conductor on the device region having a horizontal surface and substantially vertical wall surfaces;

forming a layer of Al overlying the refractory metal conductor and the dielectric layer;

reacting Al and refractory metal to form an Al alloy layer;

etching away unreacted Al from the surface of the substrate; and

oxidizing the Al alloy layer to form an Al₂ O₃ layer overlying the refractory-metal conductor, wherein the Al₂ O₃ layer overlies only the horizontal and substantially vertical wall surfaces of the refractory-metal conductor.

2. The method of claim 1 wherein the refractory-metal is selected from the group consisting of W, Mo, Cr, Co and Pt.

3. The method of claim 1 wherein the semiconductor device is one of a DRAM, SRAM, data processor device or Bi-CMOS device.

4. A method for fabricating an MOS transistor gate comprising:

providing a substrate having a device region thereon;

forming a dielectric layer to overlie the substrate;

forming a gate electrode on the device region wherein the gate electrode comprises, a polysilicon layer directly overlying the dielectric layer, a TiN layer overlying the polysilicon layer and a refractory-metal layer overlying the TiN layer;

forming a layer of Al overlying the refractory gate electrode and the dielectric layer;

reacting Al and refractory metal to form an Al alloy layer;

etching away unreacted Al from the dielectric layer; and

oxidizing the Al alloy layer to form an Al₂ O₃ layer solely overlying the exposed surface regions of the refractory-metal layer.

5. A method for forming a local interconnect in a semiconductor device comprising:

forming a refractory-metal lead on a semiconductor substrate having a plurality of conductive layers thereon, the refractory-metal lead providing an electrical conduit between the plurality of conductive layers;

depositing a layer of Al to overly the refractory-metal lead and the semiconductor substrate;

applying thermal energy to react the Al layer with the refractory-metal lead to form an Al/refractory-metal alloy on the surface of the refractory-metal lead;

removing the unreacted Al from the semiconductor substrate; and

oxidizing the Al/refractory-metal alloy to form a layer of Al₂ O₃ encapsulating the refractory-metal lead.

6. The method of claim 5 wherein the refractory-metal is selected from the group consisting of W, Mo, Cr, Co and Pt.

7. A method for preventing the oxidation of a refractory-metal conductor in a semiconductor device comprising:

forming a refractory-metal conductor on a semiconductor substrate;

reacting the refractory-metal with Al to form an Al/refractory-metal alloy on the surface of the refractory-metal conductor; and

oxidizing the Al/refractory-metal alloy to form a layer of Al₂ O₃ encapsulating the refractory-metal conductor wherein the Al₂ O₃ layer provides a barrier to oxygen diffusion therethrough.

8. The method of claim 7 wherein the refractory-metal is selected from the group consisting of W, Mo, Cr, Co and Pt.

9. The method of claim 7 wherein the semiconductor device is one of a DRAM, SRAM, data processor, bi-polar device or Bi-CMOS device.

10. A method for fabricating a low resistance electrical conductor in a semiconductor device comprising:

providing a single crystal silicon substrate having a device region thereon;

oxidizing the substrate to form a silicon dioxide dielectric layer thereon;

depositing a layer of W onto the dielectric layer;

forming a photoresist pattern on the layer of W

etching the layer of W to form a W conductor over the device region of the substrate;

removing the photoresist pattern;

depositing a layer of Al onto the substrate;

annealing the substrate to selectively form a layer of WAl₁₂ between the Al layer and the W conductor and to leave an unreacted portion of the Al layer;

etching away the unreacted portion of the Al layer from the substrate; and

oxidizing the WAl₁₂ layer to selectively form a layer of Al₂ O₃ encapsulating the W conductor.

11. The method of claim 10 wherein the step of annealing the substrate to form the layer of WAl₁₂ is carried out by means of rapid thermal annealing.

12. The method of claim 10 wherein the step of oxidizing WAl₁₂ layer is carried out by means of rapid thermal annealing in an O₂ atmosphere.

13. The method of claim 10 wherein the step of depositing a layer of W is carried out by reacting WF₆ with excess H₂ in a CVD reactor.

14. A method for fabricating a high performance capacitor in a semiconductor device comprising:

providing a substrate having a device region thereon;

forming a dielectric layer to overlie the substrate;

forming a refractory-metal conductor on the device region having a horizontal surface and substantially vertical wall surfaces;

forming a layer of Al overlying the refractory metal conductor and remaining portions of the substrate;

reacting Al and refractory metal to form an Al alloy layer;

etching away unreacted Al from the surface of the substrate;

oxidizing the Al alloy layer to form an Al₂ O₃ layer overlying the refractory-metal conductor to form a capacitor dielectric wherein the Al₂ O₃ layer overlies only the horizontal and substantially vertical wall surfaces of the refractory-metal conductor; and

forming a conductive top plate overlying the Al₂ O₃ layer and aligned to the wall surfaces of the refractory metal conductor.

15. The method of claim 14 wherein the refractory-metal is selected from the group consisting of W, Mo, Cr, Co and Pt.