Method of manufacturing edge connected semiconductor die

• US 5,126,286 A
• Filed: 10/05/1990
• Issued: 06/30/1992
• Est. Priority Date: 10/05/1990
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Chance, Randal W.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US07/593,155
• Time in Patent Office: 634 Days
• Field of Search: 437/203, 437/226, 437/227
• US Class Current: 438/462
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

Die bond locations on a semiconductor die are formed as vertical inserts along the edge of the die. The vertical inserts are isolated from substrate and are exposed by a wafer saw process, in which dice are singulated from a wafer. The configuration offers the advantages of a more efficient layout, allowing the entire top surface of the die to be passivated, a better contact configuration, and more convenient assembly for packaging.

Claims

1. Method of forming an integrated circuit device having die bond locations on a perimeter of a die, the method comprising:

a) preparing a semiconductor wafer, which includes a semiconductor substrate and a plurality of dice, each die being defined by a perimeter, and having circuitry on a face of the die;

b) forming a plurality of depressions in the substrate, the depressions each extending from locations on the faces to said perimeter;

c) depositing conductive material in said depressions to form wirebond pads;

d) forming a first group of contacts, contacting said wirebond pad to said circuitry within the die;

e) passivating the dice by applying a protective dielectric over the dice; and

f) separating the dice, thereby exposing edges of said depression, with the conductive material in said depressions forming die bond locations along said exposed edges.

2. Method of forming an integrated circuit as described in claim 1, further comprising:

said depressions being formed to extend into the wafer more than 1/500 the thickness of the substrate, but less than 1/5 the thickness of the substrate.

3. Method of forming an integrated circuit as described in claim 1, further comprising:

said depressions being formed to extend into the wafer more than 1/100 the thickness of the substrate, but less than 1/10 the thickness of the substrate.

4. Method of forming an integrated circuit as described in claim 1, further comprising:

isolating the conductive material in said depressions forming die bond locations along said exposed edges from the semiconductor substrate prior to depositing conductive material in said depressions.

5. Method of forming an integrated circuit as described in claim 1, further comprising:

isolating the conductive material in said depressions forming die bond locations along said exposed edges from the semiconductor substrate, said isolation of said conductive material including forming an oxide layer in the depressions prior to depositing the conductive material in said depressions.

6. Method of forming an integrated circuit as described in claim 1, further comprising:

isolating the conductive material in said depressions forming die bond locations along said exposed edges from the semiconductor substrate prior to depositing the conductive material in said depressions, said isolation of said conductive material including providing a layer of doped material in the depressions.

7. Method of forming an integrated circuit as described in claim 1, further comprising:

isolating the conductive material in said depressions forming die bond locations along said exposed edges from the semiconductor substrate prior to depositing the conductive material in said depressions, said isolation of said conductive material including providing a layer of doped polysilicon in the depressions.

8. Method of forming an integrated circuit as described in claim 1, further comprising:

a) providing a layer of polysilicon material in said depressions forming die bond locations along said exposed edges from the semiconductor substrate;

b) isolating the conductive material in said depressions forming die bond locations along said exposed edges from the semiconductor substrate, said isolation including forming an oxide layer in the depressions subsequent to providing said layer of polysilicon, and prior to depositing the conductive material in said depressions.

9. Method of forming an integrated circuit as described in claim 8, further comprising:

a) establishing logic circuit on the wafer in a plurality of fabrication steps, including a plurality of mask steps;

b) forming of the plurality of depressions being performed prior to completion of establishing the logic circuitry on the wafer; and

c) establishing said isolation of the conductive material in said depressions forming die bond locations along said exposed edges from the semiconductor substrate during said fabrication steps.

10. Method of forming integrated circuit electronic components, characterized by:

a) forming circuitry on a semiconductor wafer, said circuitry including die bond locations;

b) forming a passivation layer over said circuitry; and

c) exposing the die bond locations by use of a wafer saw.

11. Method of forming integrated circuit components as described in claim 10, further comprising:

a) depositing conductive material into a plurality of depressions at the die bond locations; and

b) isolating the die bond locations from the semiconductor wafer prior to depositing conductive material in said depressions.

12. Method of forming integrated circuit components as described in claim 11, further comprising:

said isolated of said conductive material including forming an oxide layer in the depression prior to depositing the conductive material in said depressions.

13. Method of forming integrated circuit components as described in claim 11, further comprising:

said isolation of said conductive material including providing a layer of doped material in the depressions.

14. Method of forming integrated circuit components as described in claim 11, further comprising:

said isolation of said conductive material including providing a layer of doped polysilicon in the depressions.

15. Method of forming integrated circuit components as described in claim 10, further comprising:

a) providing a plurality of depressions at the die bond locations;

b) providing a layer of polysilicon material in said depressions;

c) isolating the layer of polysilicon material in said depressions, said isolation including forming an oxide layer in the depressions subsequent to providing said layer of polysilicon; and

d) depositing conductive material into said depressions at the die bond locations.

16. Method of forming integrated circuit components as described in claim 10, further comprising:

a) establishing logic circuitry on the wafer in a plurality of fabrication steps, including a plurality of mask steps; and

b) establishing said isolation of the die bond locations along said exposed edges from the semiconductor wafer during said fabrication steps.