Vertical MOS transistor and its production method

• US 5,126,807 A
• Filed: 06/12/1991
• Issued: 06/30/1992
• Est. Priority Date: 06/13/1990
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Baba, Yoshiro, Osawa, Akihiko, Yanagiya, Satoshi, Hiraki, Shunichi
• Primary Examiner(s): PRENTY, MARK V
• Application Number:
  US07/713,505
• Time in Patent Office: 384 Days
• Field of Search: 357/23.4, 357/23.14, 357/23.5, 357/55
• US Class Current: 257/401
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. THE gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.

Claims

1. A vertical MOS transistor, comprising:

(a) a semiconductor substrate;

(b) a first impurity region defined on the surface of said semiconductor substrate;

(c) a second impurity region defined under said first impurity region, the conductivity type of said second impurity region being opposite to that of said first impurity region;

(d) a trench engraved on the surface of said semiconductor substrate to cut through said first and second impurity regions deeper than at least a bottom of said second impurity region;

(e) a first gate electrode disposed on a bottom of said trench with a first gate insulation film interposing between a wall of said trench and said first gate electrode; and

(f) a second gate electrode disposed over said first gate electrode in said trench with a second gate insulation film interposing between the wall of said trench and said second gate electrode,

(g) said first gate insulation film being thicker than said second gate insulation film.

2. The vertical MOS transistor according to claim 1, wherein said trench reaches said semiconductor substrate.

3. The vertical MOS transistor according to claim 1, wherein a capacitance insulation film is formed between said first and second gate electrodes.

4. The vertical MOS transistor according to claim 1, wherein said first and second gate electrodes are electrically connected to each other.

5. A vertical MOS transistor, comprising:

(a) a semiconductor substrate;

(b) a first impurity region defined on the surface of said semiconductor substrate;

(c) a second impurity region defined under said first impurity region, the conductivity type of said second impurity region being opposite to that of said first impurity region;

(d) a trench engraved on the surface of said semiconductor substrate to cut through said first and second impurity regions deeper than at least the bottom of said second impurity region;

(e) a floating gate electrode disposed on the bottom of said trench with a first gate insulation film interposing between a wall of said trench and said floating gate electrode; and

(f) a main gate electrode disposed over said floating gate electrode with a capacitance insulation film interposing between said floating gate electrode and said main gate electrode and with a second gate insulation film interposing between said main electrode and said first and second impurity regions,

(g) said first gate insulation film being thicker than said second gate insulation film.

6. The vertical MOS transistor according to claim 5, wherein said trench reaches said semiconductor substrate.

7. The vertical MOS transistor according to claim 5, wherein said floating gate electrode and main gate electrode are electrically connected to each other.