Multiple integrated circuit interconnection arrangement

• US 5,126,920 A
• Filed: 09/23/1991
• Issued: 06/30/1992
• Est. Priority Date: 05/01/1986
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Cardashian, Vahram S., Loy, Jerald M.
• Primary Examiner(s): Thompson, Gregory D.
• Application Number:
  US07/764,439
• Time in Patent Office: 281 Days
• Field of Search: 174/52.4, 174/254-258, 361/398, 361/400, 361/414
• US Class Current: 361/749
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0289 having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
• CPC Class Codes: H05K 1/189 characterised by the use of a flexible or folded printed circuit H05K3/326 takes precedence

Abstract

A flexible chip interconnection includes a flexible film having interconnection lines formed on opposite sides thereof, with selected of the interconnection lines from one side connected by through-film conductors to interconnection lines on the other side. Insulating layers cover both sets of interconnection lines. Multi-chip circuits can be formed on the film with the interconnection lines directly connecting the chips.

Claims

1. A self-contained integrated circuit interconnect package adapted to be incorporated into an electrical or electromechanical device, wherein the device includes a printed wiring board with circuit connecting means for connecting to said package, comprising:

a flexible, thin electrical insulating film, having first and second openings therethrough, and having first and second oppositely disposed surfaces;

a first set of electrical interconnection lines, located on said first surface and including first and second integrated circuit connection sites;

a second set of electrical interconnection lines located on said second surface;

first and second electrical insulating layers covering said first and second surfaces, respectively, except at selected contact locations;

first and second integrated circuits, wherein said first integrated circuit is connected to said first integrated circuit connection cite by wire bonds, and said second integrated circuit is connected to said second integrated circuit site by wire bonds;

a set of interconnections for external circuits on said second surface, wherein some of said interconnections for external circuits are electrically connected to at least one of said first set of electrical interconnection lines or to at least one of said second set of electrical interconnection lines;

first and second electrical connection through-films, located respectively in said first and second openings, wherein said through-films connect at least one of said first set of electrical interconnections which is connected to said first site to at least one of said second set of electrical interconnections which is connected to said second site, by way of at least one said second set of electrical interconnection lines, to thereby provide an electrical signal path between said intergrated circuit connection sites; and

wherein some of said interconnections for external circuits are adapted to be directly connected to the circuit connecting means.

2. The package of claim 1 wherein said wire bonds are formed by thermo-compression bonding.

3. The package of claim 1 wherein said wire bonds are formed by ultrasonic bonding.

4. The package of claim 1 wherein the majority of said interconnection lines are no more than 2 mils wide, and some of said interconnection lines are spaced as close as 2 mils, edge to edge.