Discrete cosine transform processing system

• US 5,126,962 A
• Filed: 07/11/1990
• Issued: 06/30/1992
• Est. Priority Date: 07/11/1990
• Status: Expired due to Term

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Chiang, Alice M.
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US07/551,871
• Time in Patent Office: 720 Days
• Field of Search: 364/725, 364/604, 364/826, 382/56
• US Class Current: 708/401
• CPC Class Codes: G06F 17/147 Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform G06F17/145 takes precedence
• CPC Class Codes: H04N 19/62 by frequency transforming in three dimensions H04N19/63 takes precedence
• CPC Class Codes: H04N 19/649 the transform being applied to non rectangular image segments

Abstract

A three dimensional (3D) discrete cosine transform (DCT) uses one dimensional DCT networks for transforming and inverse-transforming blocks of data, such as image data. The 3D DCT configuration uses DCT transform coding to remove both the spatial and temporal redundancy of a sequence of image frames to achieve high bandwidth compression.

Claims

1. A data processing system comprising:

A. a first 1D DCT network, said first DCT network having an i-value parallel data input channel for receiving a succession of parallel data words applied thereto, each word having up to i data values, and having a j-value parallel data output channel, and including means for transforming said applied data words in accordance with a one dimensional discrete cosine transformation (DCT) to generate a succession of parallel DCT data words, each word being associated with one of said applied data words and having a plurality of data values, and for applying said succession of parallel DCT data words to said output channel,

B. a corner turning memory network having a j-value parallel data input channel, an i-value parallel data output channel, and an i×

j cell rectangular array of data storage locations, each location being adapted to store a data value, said locations extending in the direction of an input axis from a j cell input edge of said array, and extending in the direction of an output axis to an i cell output edge of said array, said output axis being orthogonal to said input axis,

wherein said locations at said input edge are coupled to receive data values in parallel from said parallel data input channel, and said locations at said output edge are coupled to transfer data values in parallel to said parallel output channel,

wherein said array includes first means for selectively transferring stored data values from each of said locations to the adjacent locations in said array in the direction of said input axis, and includes second means for selectively transferring said stored data values from each of said locations to the adjacent locations in said array in the direction of said output axis, and

wherein said array further includes a corner controller having means for controlling said first and second transferring means of said array to be operative alternately to load said locations with a succession of data words from said parallel data input channel and to unload said locations and apply a succession of data words to said parallel data output channel,

C. a second 1D DCT network, said second DCT network having an i-value parallel data input channel for receiving a succession of parallel data words applied thereto, each word having up to i data values, and having a j-value parallel data output channel, and including means for transforming data words applied to said parallel data input channel in accordance with a one dimensional discrete cosine transformation (DCT) to generate a succession of parallel DCT data words, each being associated with one of said applied data words and having a plurality of values and for applying said succession of parallel DCT data words to said output channel,

D. means for coupling said output channel of said first DCT network to said input channel of said corner turning memory network, and

E. means for coupling said output channel of said corner turning memory network to said input channel of said second DCT network.

2. A system according to claim 1 further comprising:

F. a cube turning memory network having;

an i×

j stage serial-in/parallel-out input data shift register adapted to receive a succession of j i-value serial data words and to transfer out a succession of i×

j value parallel data words,

a k stage parallel-in/parallel-out output data buffer including means for selectively receiving a succession of k-value parallel data words and for selectively transferring out a succession of k-value parallel data words,

an i×

j×

k cell rectangular array of data storage locations, each location being adapted to store a data value, said locations extending in the direction of an input axis from an i×

j cell input edge of said array, and extending in the direction of an output axis to a k cell output edge of said array, said output axis being orthogonal to said input axis,

wherein said locations at said input edge are coupled to receive data in parallel from said input shift register, and said locations at said output edge are coupled to transfer data in parallel to said output buffer,

wherein said array includes first means for selectively transferring stored data values from each of said locations to the adjacent locations in said array in the direction of said input axis, and includes second means for selectively transferring said stored data values from each of said locations to the adjacent locations in said array in the direction of said output axis, and

wherein said array further includes a cube controller having means for controlling said first and second transferring means of said array to be operative alternately to load said locations with a succession of data words from said input shift register and to unload said locations and apply a succession of data words to said output buffer,

G. a third 1D DCT network, said third DCT network having a k-value parallel data input channel for receiving a succession of parallel data words applied thereto, and an 1-value parallel data output channel, and including means for transforming data words applied to said parallel data input channel in accordance with a one dimensional cosine transformation (DCT) to generate a succession of parallel DCT data words and for applying said parallel DCT data words to said output channel, and

H. means for coupling said output shift register of said cube turning memory network to said input channel of said third DCT network, said coupling means including means for applying said K-value data words in parallel to said parallel input channel of said third DCT network.

3. A system according to claims 1 or 2 wherein said values are represented by analog signals comprising a plurality of charge packets, and wherein said first DCT network, said second DCT network, and said corner turning memory network are charge coupled devices (CCD'"'"'s).

4. A system according to claims 1 or 2 further comprising:

A. an i-stage serial-in/parallel-out input data shift register, said shift register having a serial data input channel adapted to receive a succession of i-value serial input data words, and said shift register having a i-value parallel data output channel coupled to the respective stages of said shift register, and

B. means for coupling said output channel of said shift register to said input channel of said first DCT network.

5. A system according to claim 4 wherein said values are represented by analog signals comprising a plurality of charge packets, and wherein said shift register is a charge coupled device (CCD).

6. A system according to claim 4 wherein said third DCT network and said cube turning memory network are charge coupled devices (CCD'"'"'s).

7. A cube turning memory network having:

an i×

j stage serial-in/parallel-out input data shift register adapted to receive a succession of j i-value serial data words and to transfer out a succession of i×

j value parallel data words,

a k stage parallel-in output data shift register adapted to receive a succession of k-value parallel data words and to transfer out a succession of k-value data words,

an i×

j×

k cell rectangular array of data storage locations, each location being adapted to store a data value, said locations extending in the direction of an input axis from an i×

j cell input edge of said array, and extending in the direction of an output axis to a k cell output edge of said array, said output axis being orthogonal to said input axis,

wherein, said locations at said input edge are coupled to receive data in parallel from said input shift register, and said locations at said output edge are coupled to transfer data in Parallel to said output shift register,

wherein said array includes first means for selectively transferring stored data values from each of said locations to the adjacent locations in said array in the direction of said input axis, and includes second means for selectively transferring said stored data values from each of said locations to the adjacent locations in said array in the direction of said output axis, and

wherein said array further includes a cube controller having means for controlling said first and second transferring means of said array to be operative alternately to load said locations with a succession of data words from said input shift register and to unload said locations and apply a succession of data words to said output shift register.

8. A system according to claim 7 wherein said values are represented by analog signals comprising a plurality of charge packets, and wherein said input shift register, said output shift register, and said array are charged coupled devices (CCD'"'"'s).