Writable distributed non-volatile analog reference system and method for analog signal recording and playback

• US 5,126,967 A
• Filed: 09/26/1990
• Issued: 06/30/1992
• Est. Priority Date: 09/26/1990
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Information Storage Devices, Inc. (Winbond Electronics Corporation)
• Inventors: Simko, Richard
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/589,173
• Time in Patent Office: 643 Days
• Field of Search: 365/45, 365/210, 365/189.09
• US Class Current: 365/45
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

A writable distributed non-volatile analog reference system and method for analog signal recording and playback having application in integrated circuits which sample and directly store analog information. The invention is useful to facilitate the sensing of analog levels stored in nonvolatile memory cells where the analog levels are played back such as to reproduce voice or music or tone information. In accordance with the method, one or more reference storage columns are included in the array at each side of the storage cell array and are used to store a reference signal at the same time that the adjacent storage cell stores a signal sample. On playback, the stored reference signals for the row of the array are read back and weighted relative to each other in accordance with the relative row position of the signal storage cell being simultaneously read, with the output signal being taken as the difference between the signal sample read back and the reference signals read back (as weighted relative to each other as per the position in the row of the signal cell). This differencing places many error sources in the common mode, thereby substantially eliminating the same from the output signal. A specific memory array organization and the operation thereof is disclosed.

Claims

1. A reference system for an integrated circuit analog recording and playback device having an array of columns and rows of analog signal sample storage cells wherein a plurality of samples of an analog signal are temporarily held in sample and hold circuits distributed across the array and then parallel loaded into a plurality of sample storage cells of the array comprising:

at least one column of reference storage cells at each side of the array of analog signal sample storage cells;

a sample and hold circuit coupled to each column of reference storage cells;

reference means for generating a fixed reference voltage;

means for causing a reference voltage to be sampled by a respective sample and hold circuit coupled to a column of reference storage cells whenever the adjacent sample and hold circuit samples the analog signal for subsequent storage in a sample storage cell;

means for causing the sampled reference voltage held in a sample and hold circuit coupled to a column of reference storage cells to be written into a reference storage cell of a particular cell row when the signal sample held in the adjacent sample and hold circuit is written into a storage cell of the corresponding row of analog signal sample storage cells of the array;

means for causing the sampled reference voltages stored in the reference storage cells to be read from the reference storage cells of a particular cell row when a signal sample stored in any signal storage cell of the corresponding row of analog signal sample storage cells of the array is read out of the array;

means for providing cell reference voltages from the reference voltages read from the reference storage cells each cell reference voltage corresponding to the position along a row of the signal storage cell currently being read; and

,

means for taking the difference between the signal sample read out of a cell of the array and the respective cell reference voltage.

2. The reference system of claim 1 having a plurality of sample and hold circuits, each being coupled to a plurality of columns of analog signal sample storage cells through a multiplexer, whereby a sample and hold circuit is coupled to each column of reference storage cells at different times dependent on the state of the multiplexer.

3. The reference system of claim 1 wherein said means for providing a cell reference voltage by combining the reference voltages read from the reference storage cells with a relative weighting dependent upon the position along a row of the signal storage cell currently being read comprises:

(a) a resistor having one end connected to the sampled reference voltage read from the reference storage cell at one side of a particular cell row of the array and the other end connected to the sampled reference voltage read from the reference storage cell at other side of a particular cell row of the array; and

,

(b) means for tapping the voltage from positions along said resistor in proportion to the relative position along a cell row of the signal storage cell currently being read.

4. A method of storing an analog signal in an array of columns and rows of integrated circuit signal storage cells wherein an analog signal is periodically sampled and each sample held in a sample and hold circuit until a predetermined number of samples have accumulated, and then the predetermined number of samples taken and held is written into a row of the memory array, comprising the steps of:

(a) providing a reference voltage;

(b) providing for each row of integrated circuit signal storage cells, a first and second integrated circuit reference storage cells;

(c) sampling and holding the reference voltage in a first reference voltage sample and hold circuit when the first of the predetermined number of samples of the analog signal is taken and held in a sample and hold circuit;

(d) sampling and holding the reference voltage in a second reference voltage sample and hold circuit when the last of the predetermined number of samples of the analog signal is taken and held in a sample and hold circuit; and

,

(e) writing the samples of the reference voltage held in the first and second reference voltage sample and hold circuits into first and second reference voltage storage cells when the predetermined number of signal samples taken and held is written into associated signal storage cells for the respective row of the memory array.

5. The method of claim 4 further comprised of the steps of:

(f) reading the sampled reference voltages stored in the reference storage cells from the reference storage cells of a particular cell row when a signal sample stored in any signal storage cell of the corresponding row of analog signal sample storage cells of the array is read out of the array;

(g) determining cell reference voltages from the reference storage cells, each cell reference voltage corresponding to the relative time the respective signal sample was taken and held in comparison to the times the respective reference voltage samples were taken and held; and

;

(h) taking the difference between the signal sample read out of a cell of the array and the respective cell reference voltage to provide a signal sample output.

6. The method of claim 5 wherein the first and second reference voltage storage cells are disposed in columns along the left side and right side of the array, respectively, substantially as an extension of the array.

7. The method of claim 5 wherein the reference voltage storage cells are substantially the same as the signal storage cells and the reference voltage sample and hold circuits are substantially the same as the signal sample and hold circuits.

8. The method of claim 7 further comprised of additional storage cells disposed in columns along the left side and right side of the first and second reference voltage storage cells, respectively, also substantially as an extension of the array.