Static random access memory with PMOS pass gates

• US 5,126,970 A
• Filed: 04/06/1990
• Issued: 06/30/1992
• Est. Priority Date: 04/06/1990
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Ul Haq, Ejaz
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/505,730
• Time in Patent Office: 816 Days
• Field of Search: 365/154, 365/156, 365/181, 365/190, 365/207, 365/208, 365/230.03
• US Class Current: 365/154
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

An SRAM uses PMOS column pass gates in conjunction with PMOS column loads which can be selectively deactivated during write operations. Address decoding for the pass gates and loads can be done outside of the memory array to maximize device density. This arrangement provides densities comparable to those achievable with NMOS column pass gates, but without the read access time penalties associated therewith.

Claims

1. A static random access memory device comprising:

plural memory cells including a first memory cell;

data port means for coupling said memory cells to a host system so as to permit reading operations and writing operations therebetween, said data port means including at least a first data port;

plural bit lines means for conveying data to and from said memory cells, said plural bit line means including a first true bit line and a first false bit line for conveying data to and from said first memory cell to said data port means;

bit line means for supplying current to said plural bit lines, said load means including first load means for supplying current to said first true and false bit lines;

PMOS pass gate means for selectively coupling said plural bit line means to said data port means, said PMOS pass gate means including a first true PMOS pass gate that when activated couples said first true bit line to said first data port, and a first false PMOS pass gate that when activated couples said first false bit line to said first data port, said PMOS pass gate

when said first memory cell is selected in a write operation, directing data from said first data port means, through said first true and false PMOS pass gates, and through said first true and false bit lines for storage in said first memory cell, and

when said first memory cell is selected in a read operation, directing data from said first memory cell, through said first true and false bit lines, through said first true and false PMOS pass gates, and to said first data port means; and

address means for selecting among said memory cells for coupling to said host system and for alternatively selecting between reading and writing operations for the memory cells so addressed, said address means being coupled to said plural bit line load means and said PMOS pass gate means so as to

when said first memory cell is selected, activate said first true PMOS pass gate and said first false PMOS pass gate, and

when said first memory cell is selected and a write operation is selected, deactivate said first load means so that said first load means supplies at most negligible current to said first true and false bit lines.

2. A static random access memory device as recited in claim 1 wherein said bit line load means includes PMOS transistors.

3. A static random access memory device comprising:

an array of memory cells, said array defining a rectangular area containing said memory cells, said array having its memory cells arranged in rows and columns;

data port means for coupling said memory cells to a host system so as to permit reading operations and writing operations therebetween;

plural bit lines for conveying data to and from said memory cells, said plural bit line means including a respective true bit line and a respective false bit line for each of said columns for conveying data to and from a selected memory cell in that column;

plural bit line load means for supplying current to said plural bit lines, said plural bit line load means including a respective true and a false bit line load for each of said columns;

PMOS pass gate means for selectively coupling said columns to said data port means, for each of said columns, said PMOS pass gate means including

a respective true PMOS pass gate which, when activated, couples the respective true bit line to said data port means, and

a respective false PMOS pass gate which, when activated, couples the respective false bit line to said data port means,

said PMOS pass gate means

when one of said memory cells is selected in a write operation, directing data from said first data port means, through respective true and false PMOS pass gates, and through said respective true and false bit lines for storage in said memory cell, and

when said memory cell is selected in a read operation, directing data from said memory cell, through respective true and false bit lines, through said first true and false PMOS pass gates, and to said data port means;

word line means for selectively coupling a row of memory cells to their respective true and false bit lines; and

address means for selecting among said memory cells for coupling to said host system and for alternatively selecting between reading and writing operations for the memory cells so addressed, said address means being coupled

to said word line means for coupling a selected memory cell in a column to the respective true and false bit lines for that column,

to said PMOS pass gate means for activating the respective true and false PMOS pass gates for that column, and

to said bit line load means so that, when a write operation is selected, said address means can deactivate the respective true and false bit line loads for that column, but not for another of said columns, so that they supply at most negligible current to said respective true and false bit lines.

4. A memory device as recited in claim 3 wherein each of said PMOS pass gates has a respective control gate, the voltage at which determines the activation status of the including PMOS pass gate, and wherein said address means includes gate decoding logic for decoding received address codes into voltage levels applied to said control gates, all of said gate decoding logic being located outside said rectangular area.

5. A static random access memory device as recited in claim 4 wherein said memory array is divided into multiple blocks, each of said blocks including

an associated subarray of said memory cells,

associated cell rows of said cells, and

associated cell columns of said cells, each of said blocks having an associated set of sense amplifiers coupled to said data port means, each of said cell columns having a respective pair of pass gates for coupling its cells to said data port means, said gate decoding logic including multiple gate control lines, each of said gate control lines being coupled to gates in at least two of said blocks, including a first block and a second block, said address means including block select means for selectively coupling said blocks to said data port so that when said gate decoding logic couples cells in said first block to its associated sense amplifiers and couples cells in said second block to its respective sense amplifiers, said block select means can enable the sense amplifiers associated with said first block and disable the sense amplifiers associated with said second block so that cells of said first block are coupled to said data port means and cells of said second block are decoupled from said data port means.

6. A static random access memory device as recited in claim 4 wherein said bit line load means includes PMOS transistors.