Integrated cache SRAM memory having synchronous write and burst read

• US 5,126,975 A
• Filed: 10/24/1990
• Issued: 06/30/1992
• Est. Priority Date: 10/24/1990
• Status: Expired due to Term

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Handy, James E., Maas, Kelly A.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/602,507
• Time in Patent Office: 615 Days
• Field of Search: 365/189.01, 365/230.01, 365/189.02, 365/233, 365/230.08
• US Class Current: 365/189.14
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

An integrated cache memory device using SRAM cells is disclosed. The integrated cache memory has synchronized write capability and burst read capability.

Claims

1. A single integrated memory circuit device, responsive to a clock signal, an external address signal, and an external write enable signal, said external write enable signal having two states, said memory circuit device comprising:

address register means for storing said external address signal and for generating a first internal address signal;

counter means for receiving said clock signal and for generating a second internal address signal;

address logic means for receiving said first internal address and said second internal address signal and for generating a third internal address signal;

SRAM memory array means for storing a plurality of digital binary data in an array, said SRAM memory array means being operable in a read mode wherein said memory array means receives said third internal address signal and generates an internal data signal from said array in response thereto, and being operable in a write mode wherein said memory array means receives said first internal address signal and writes an external data signal into said array;

data register means for storing said internal data signal generated by said memory array means or for storing said external data signal received by said memory circuit device external thereto; and

logic means for receiving said external write enable signal and being responsive thereto wherein in one state said logic means causes said memory array means to be enabled in said write mode, synchronous with said clock signal; and

wherein in the other state said logic means causes said memory array means to be operable in said read mode, generating a plurality of internal data signals for each signal external address signal received.

2. The memory circuit device of claim 1 wherein said logic means further comprising:

means for generating an internal write enable signal in one state, in response to said external write enable signal being in one state and said clock signal;

means for supplying said internal write enable signal to said memory array means; and

said memory array means responsive to said internal write enable signal being in said one state to be operable in said write mode.

3. The memory circuit device of claim 2 wherein said logic means further comprising:

means for generating an internal write enable signal in another state, in response to said external write enable signal being in another state; and

said memory array means responsive to said internal write enable signal being in said another state to be operable in said read mode.

4. A single integrated memory circuit device comprising:

means for receiving an external address signal supplied to said memory circuit device, external thereto;

means for receiving a clock signal supplied to said memory circuit device, external thereto;

means for receiving an external write enable signal, supplied to said memory circuit device, external thereto, said external write enable signal having two states;

address register means for storing said external address signal;

SRAM memory array means for storing a plurality of digital binary data in an array;

said memory array means being operable in two states and is responsive to an internal write enable signal having said two states;

said memory array means in a read state is responsive to an internal address signal and generates a plurality of internal data signals from said array in response thereto, and in a write state is responsive to said internal address signal and stores said internal data signal into said array; and

logic means responsive to said clock signal, said external address signal, and said external write enable signal, and for generating said internal write enable signal and said internal address signal;

wherein said logic means in one state generates said internal write enable signal synchronous with said internal address signal and causes said memory array means to be operable in said write state, and wherein said logic means in another state generates a plurality of internal address signals in response to a single external address signal received and causes said memory array means to be operable in said read state.

5. The memory circuit device of claim 4 wherein said logic means further comprising:

counter means for receiving said clock signal and for generating an incrementing signal; and

means for combining said incrementing signal with said external address signal to produce said internal address signal.

6. The memory circuit device of claim 4 wherein said logic means further comprising:

means for receiving said external address signal from said address register means and for supplying said external address signal to said combining means.

7. The memory circuit device of claim 6 wherein said combining means is an exclusive OR gate.

8. An integrated cache memory device for use with a processor supplying an external address signal, a clock signal and an external write enable signal;

said memory device comprising;

address register means for storing said external address signal and for providing an internal address signal;

static random access memory means for storing a plurality of digital binary data in an array, said memory means being operable in a read mode and in a write mode;

logic means responsive to said external write enable signal, said internal address signal, and said clock signal, and for causing said memory means to be operable in said write mode;

said logic means further for receiving said internal address signal and responsive to said external write enable signal and said clock signal for causing said memory means to be operable in said read mode for providing a plurality of digital binary data from said array in response to a single external address signal.